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Browsing Conference Publications by Department "Universiti Malaysia Perlis"
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PublicationA Fuzzy-Based Angle-of-Arrival Estimation System (AES) using Radiation Pattern Reconfigurable (RPR) antenna and modified gaussian membership function( 2019)
;R. Badlishah, Ahmad ;Mohd Haizal Jamaluddin ;Muhammad Ramlee Kamarudin ;L. Murukesan LoganathanSoh Ping JackAngle-of-arrival (AOA) estimation is an important factor in various wireless sensing applications, especially localization systems. This paper proposes a new type of AOA estimation sensor node, known as AOA-estimation system (AES) where the received signal strength indication (RSSI) from multiple radiation pattern reconfigurable (RPR) antennas are used to calculate the AOA. In the proposed framework, three sets of RPR antennas have been used to provide a coverage of 15 regions of radiation patterns at different angles. The salient feature of this RPR-based AOA estimation is the use of Fuzzy Inferences System (FIS) to further enhance the number of estimation points. The introduction of a modified FIS membership function (MF) based on Gaussian function resulted in an improved 85% FIS aggregation percentage between the fuzzy input and output. This later resulted in a low AOA error (of less than 5%) and root-mean- square error (of less than 8◦ ).1 11 -
PublicationA novel double Co-Transformation for a simple and memory efficient logarithmic number system( 2020)
;M. S. S. M. BasirTo date, co-transformation architecture is typically used in resolving the singularity issue in the logarithmic number system (LNS). The co-transformation was first introduced by Coleman, by using a rule of sign(r 1 ) ≠ sign(r 2 ) which translate the singularity into an argument that can be stored in two identical look-up tables (LUTs) with size of 2k. Recently, a portable 32-bit chipset preferred a small LUT, hitherto a co-transformation architecture is rearranged. This paper presents a novel double co-transformation, by means of first-order co-transformation architecture that covers -0.5 <; r <; 0 region is extended to r > -1 to replace the triumvirate F, D and E tables occupy by the interpolator. The accuracy settings at the co-transformation is compromised with the worst case error of 0.5 ulp. The outcome revealed a double co-transformation with Lagrange interpolator shows a decline in the total bit by 13% compared to European Logarithmic Microprocessor (ELM). With a simple architecture, the proposed double co-transformation is a promise for a fast LNS system. -
PublicationA Real-Time distance prediction via deep learning and microsoft kinect( 2022)
;Hwee Sheng Tham3D(Dimension) understanding has become the herald of computer vision and graphics research in the era of technology. It benefits many applications such as autonomous cars, robotics, and medical image processing. The pros and cons of 3D detection bring convenience to the human community instead of 2D detection. The 3D detection consists of RGB (Red, Green and Blue) colour images and depth images which are able to perform better than 2D in real. The current technology is relying on the high costing light detection and ranging (LiDAR). However, the use of Microsoft Kinect has replaced the LiDAR systems for 3D detection gradually. In this project, a Kinect camera is used to extract the depth of image information. From the depth images, the distance can be defined easily. As in the colour scale, the red colour is the nearest and the blue colour is the farthest. The depth image will turn black when reaching the limitation of the Kinect camera measuring range. The depth information collected will be trained with deep learning architecture to perform a real-time distance prediction. -
PublicationA review on harmonic mitigation method for non-linear load in electrical power system( 2021)
;Muhammad Mokhzaini Azizan -
PublicationA review on harmonic mitigation method for non-linear load in electrical power system( 2021)
;Muhammad Mokhzaini Azizan -
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PublicationAn Analysis of Interpolation Implementation for LNS Addition and Subtraction Function in Positive RegionInterpolation is among of the most popular approach used in approximating the values in logarithmic number system (LNS) arithmetic design. This method that often combines with lookup tables (LUTs) manages to produce efficient LNS design in area, latency and accuracy. Current research proves that the combination of interpolators with co-transformation in LNS subtraction had shown extreme improvements in terms of speed and area, which is comparable to floating point (FLP) performance. Taking the advantage, this research had been conducted to analyze the implementation of these three interpolators, which are Taylor, Lagrange and modified Lagrange, in a 32-bit environment of the LNS addition and subtraction procedures with the first-order co-transformation in positive region. The designs were analyzed in two categories, which are the accuracy towards FLP and the total memory consumption. The best interpolator was selected based on the most optimum area consumption design with manageable accuracy in FLP limit. The outcome of this analysis could benefit further improvements in LNS design.
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PublicationAn Investigation of Extended Co-Transformation using Second-Degree Interpolation for Logarithmic Number System( 2020)
;M. S. S. M. BasirThis paper addresses the proposal of improved logarithmic number system (LNS) with extended co-transformation and memory efficient second-degree Newton interpolator. Since the current interpolation with extension requires 4 look-up tables (LUTs), improvement is proposed to achieve requirement by employing only 3 LUTs with small silicon area. It was found that with the proposed extended co-transformation, a set of interpolation LUT that covered region-1 < r <-0.5 could be eliminated. Results from GNU simulator indicated that the maximum error for the proposed Newton interpolation was 9% lower compared to other current interpolators, although the total memory was unsatisfactory. An Implementation shows an efficient memory for a new LNS system, hence benefited for a dynamic real-time computation -
PublicationAnalysis of FXP adders and multipliers for speed- and area-efficient LNS arithmetic unit( 2014)J. N. ColemanThis paper portrays the selection of hardware unit architectures to be implemented in the new LNS based on a 32bit system. The implementations of the LNS multiply and divide only require a FXP adder, while the LNS addition and subtraction function comprised of several memories, FXP adders and multipliers together with other supporting logics. Thus, in choosing the best FXP adders and multipliers, each of the arithmetic is functionally verified and synthesised using Synopsys Design Compiler in Faraday 0.18 μm CMOS technology based on a 32-bit system. Two types of performance measurement, which are the worst-case delay and the silicon area, are chosen as the evaluation arguments. From conducted analytical studies, the CLA/CSLA adder and Booth recoded with Wallace tree multiplier were the best FXP adder and multiplier blocks to be applied in the system since they were the fastest designs. Using these blocks, the synthesis of the LNS system produced an approximately 7.10 ns of critical delay for addition and subtraction, and solely 1.16 ns for multiplication and division. The total area for a complete LNS architecture was 599,871 μm2, in which 65% the size of previously designed LNS architecture of ELM. © 2014 IEEE.
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PublicationArithmetic addition and subtraction function of logarithmic number system in positive region: An investigationLogarithmic number system or LNS has become an optimal choice in digital image processing instead of floating point (FP) system based on latest researches in LNS. Digital image processing which deals with a lot of complex operations such as multiplication and division, makes LNS as a great choice of implementation. However, the implementation had been restricted by the addition and subtraction function in LNS arithmetic as these functions entail complex procedures and circuitry. As its huge potential to be a substitution of FP, there is an urgent need for LNS to improve the performance of both operations. Hence, various studies had been conducted in this area, however most of the research concern the implementation of these operations in the negative region. Therefore, this study is conducted with the objective on the exploration of both LNS addition and subtraction operations in the positive region and highlights the potential areas for design modifications and improvements. Then, these enhancements will be combined with other arithmetic functions in creating an optimum LNS design to be utilized in any digital image processing system.
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PublicationAssessing Virtual Reality Sickness in Highly Immersive Virtual Laboratory Environments : Simulator Sickness Questionnaire and Mitigation Strategies( 2023)
;Ahmed Jamah Ahmed Alnagrat ;Abdulaziz E Salem Shagluf ;Rajaa. F. Mahmoud Sulieman ;Abubaker Almintisir Abubaker AkeelVirtual Reality (VR) sickness, a common challenge among VR users, has increasingly gained attention in academic research due to its adverse side effects. The Simulator Sickness Questionnaire (SSQ) has been traditionally employed to measure simulator motion sickness; however, the extent to which it measures symptoms specifically attributable to VR sickness remains underexplored. This study investigates the applicability of SSQ in assessing VR sickness in a virtual semiconductor laboratory environment, with a focus on reducing motion sickness in VR devices. A total of 97 participants performed target selection tasks using HP Reverb G2 and Oculus Quest 2 headsets in a virtual laboratory setting. The original SSQ was revised to create a VR Sickness Questionnaire, which served as the measurement index for VR-induced symptoms. The primary objective of this research was to determine the prevalence of VR sickness and explore ways to mitigate motion sickness in VR devices. The Results indicate that the majority of VR-related side effects pertain to nausea dysfunction, with a limited number of symptoms linked to cybersickness arising from various factors. These findings hold significant implications for future studies aiming to measure and design interventions for simulator sickness in VR environments. By shedding light on the effectiveness of the SSQ for evaluating VR sickness, this study contributes to the development of improved VR experiences and technologies. -
PublicationAutomated tomato grading system using Computer Vision (CV) and Deep Neural Network (DNN) Algorithm( 2022-01-01)
;Tan Wei Keong ;Muhammad Amir Hakim IsmailMuhammad Luqman YasruddinThe tomato grading is based on the skin colour at the grading stage. The evaluation of the colour used to classify tomatoes is very important, and the current methods of identifying and determining tomato varieties are still manual and prone to human error. The ability to automate tomato grading helps the food industry determine colour grades during the evaluation phase. Therefore, Computer Vision (CV) and Deep Neural Network (DNN) are utilised to grade tomatoes by determining their maturity colour. Three hundred tomatoes were selected and its maturity level are assigned by expertise. The tomato images are captured, processed and passed to the DNN classifier to determine the tomato grade. The proposed DNN classifier achieved the mAP percentage of 95.52%. This shows that the computer vision built into the DNN algorithm can provide an efficient implementation for predicting tomato grade.3 1 -
PublicationBiological sequence alignments: A review of hardware accelerators and a new PE computing strategy( 2014)Khaled BenkridOne of the most challenging tasks in sequence alignment is its repetitive and time-consuming alignment matrix computations. In addition, performing sequence alignment in hardware, i.e. FPGA requires more hardware resources as the number of processing elements is replicated to increase performance throughput. This paper first reviews the existing FPGA-based biological sequence alignment core architectures and then proposed an efficient scheduling strategy, the so-called overlap computation and configuration (OCC) towards realizing optimized biological sequence alignment core architecture targeting for pairwise sequence alignment. In this research work, double buffering-based core architecture have been proposed and implemented on Xilinx Virtex-5 FPGA. Results have shown that this approach gained more than 10K times speed-up as compared to the GPP solution.
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PublicationBreast surface variation phase map analysis with digital fringe projection( 2019)
;Wan Mokhzani Wan Norhaimi ;Mukhzeer Mohamad Shahimin ;MAM Azmi ;K Wong ;Vithyacharan Retnasamy ;Rajendaran Vairavan ;Christopher R. ValentaMasafumi Kimata -
PublicationCharacterization of silica powder prepared from acid leaching and thermal treatment of RHA( 2024)
;Mudrikah Sofia Mahmud ;Farah Diana Mohd Daud ;Norshahida Sarifuddin ;Hafizah Hanim Mohd Zaki ;Norhuda Hidayah Nordin -
PublicationCorrelation of film thickness to optical band gap of Sol-gel derived Ba0.9Gd0.1TiO3 thin films for optoelectronic applications( 2017)
;Yen Chin Teh ;Ala’eddin A. SaifBa0.9Gd0.1TiO3 thin films have been fabricated on SiO2/Si and fused silica by sol-gel method. The films are prepared through a spin coating process and annealed at 900 °C to obtain crystallized films. The effect of film thickness on the microstructure and optical band gap has been investigated using X-ray diffractometer, atomic force microscope and ultraviolet-visible spectroscopy, respectively. XRD patterns confirm that the films crystallized with tetragonal phase perovskite structure. The films surface morphology is analysed through amplitude parameter analysis to find out that the grain size and surface roughness are increased with the increase of films thickness. The transmittance and absorbance spectra reveal that all films exhibit high absorption in UV region. The evaluated optical band gap is obtained in the range of 3.67 - 3.78 eV and is found to be decreased as the thickness increase. -
PublicationCritical analysis of stability and performance of organometal halide perovskite solar cells via various fabrication method (Review)( 2017)
;Suriati Suhaimi ;Vithyacharan RetnasamyMukhzeer Mohamad ShahiminOrganometal halide perovskite solar cells (Omh-PSCs) have attracted attention due to its unique electrical and optical properties. Ideally, the Omh-PSCs should remain free from degradation under normal operating conditions for several years, preferably tens of years. In order to produce high power conversion efficiency with low potential of degradation, different fabrication methods have been developed. The reported stability of perovskite films can vary significantly and reported to decay substantially up to 20% of its original performance. A thorough understanding of fabrication process upon the stability of the device is regarded as crucial to pave the way for future endeavors. This review summarized and highlighted the recent research of fabrication methods that gave an impact to the stability of perovskite devices. -
PublicationDesign and analysis of a two-stage OTA for sensor interface circuit( 2014)
;Siti Nur Syuhadah BaharudinThis paper discusses the design of an operational transconductance amplifier (OTA) circuit foruse in a capacitive sensor interface circuit. The OTA converts a differential voltage input into the current as part of a switched capacitor integrator module. In this paper, a two-stage OTA is proposed which has high gain, high output swing and low noise. The circuit wasimplemented using 0.13μm Silterra CMOS technology and simulated using the Mentor Graphic Design Architect software package. The results show that the OTA is able to achieve74dB gain and 20KHz bandwidth when operated using a 2.5V power supply, with a total power consumption of 1.3mW. © 2014 IEEE. -
PublicationDesign and comparison of 8-bit hybrid and fixed point arithmetic unit( 2020)
;Premganesh SugumaranAn arithmetic unit of the arithmetic logic unit (ALU) plays a significant role in performing arithmetic operations. Most of the recent arithmetic units are implemented based on floating point (FLP) or fixed point (FXP) systems. However, the multiplication and division operation of FLP and FXP systems have some restriction in offering the best performance on speed and area compared to their excellent performance of their addition and subtraction operations. Hence, the hybrid arithmetic unit is an option to offer as it combines the strength of the FXP system for the addition and subtraction operation and logarithmic number system (LNS) for the multiplication and division operation. LNS has the advantage in performing multiplication and division function by substituting these operations into FXP addition and subtraction respectively. Hence, this work presented an 8-bit hybrid arithmetic unit design that performs on four main arithmetic operations: addition, subtraction, multiplication and division. The multiplication and division operations are carried out under LNS by utilizing the Mitchell algorithm, while the addition and subtraction functions are conducted in FXP system. Both hybrid and FXP arithmetic unit are designed with suitable adders, multiplexers and combinational logics. Both arithmetic units are compared in terms of various hardware parameters such as area, cell, timing and power. Both designs are described in Verilog hardware description language (HDL) and functionally simulated and verified using the ModelSim software. The design were then been synthesized using the Synopsys Design Compiler in 0.13 µm TSMC technology. The synthesis results had proven that the designed hybrid arithmetic unit offers better performance compared to FXP arithmetic unit as it produced smaller area, higher speed, less timing and lower power consumption than the FXP arithmetic unit. As a conclusion, the hybrid arithmetic unit is more efficient and profitable than the solely used FXP arithmetic unit.