An arithmetic unit of the arithmetic logic unit (ALU) plays a significant role in performing arithmetic operations. Most of the recent arithmetic units are implemented based on floating point (FLP) or fixed point (FXP) systems. However, the multiplication and division operation of FLP and FXP systems have some restriction in offering the best performance on speed and area compared to their excellent performance of their addition and subtraction operations. Hence, the hybrid arithmetic unit is an option to offer as it combines the strength of the FXP system for the addition and subtraction operation and logarithmic number system (LNS) for the multiplication and division operation. LNS has the advantage in performing multiplication and division function by substituting these operations into FXP addition and subtraction respectively. Hence, this work presented an 8-bit hybrid arithmetic unit design that performs on four main arithmetic operations: addition, subtraction, multiplication and division. The multiplication and division operations are carried out under LNS by utilizing the Mitchell algorithm, while the addition and subtraction functions are conducted in FXP system. Both hybrid and FXP arithmetic unit are designed with suitable adders, multiplexers and combinational logics. Both arithmetic units are compared in terms of various hardware parameters such as area, cell, timing and power. Both designs are described in Verilog hardware description language (HDL) and functionally simulated and verified using the ModelSim software. The design were then been synthesized using the Synopsys Design Compiler in 0.13 µm TSMC technology. The synthesis results had proven that the designed hybrid arithmetic unit offers better performance compared to FXP arithmetic unit as it produced smaller area, higher speed, less timing and lower power consumption than the FXP arithmetic unit. As a conclusion, the hybrid arithmetic unit is more efficient and profitable than the solely used FXP arithmetic unit.
