Razaidi Hussin
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Razaidi Hussin
Official Name
Razaidi, Hussin
Alternative Name
Hussin, R.
Razaidi, Hussin
Hussin, Razaidi Bin
Hussin, Razaidi
Razaidi, H.
Main Affiliation
Scopus Author ID
22634137400
Researcher ID
AAU-6856-2020

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  • Publication
    Crypto-Core Design using Camellia Cipher
    ( 2021-03-01)
    Wei Ci C.
    ;
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Razaidi Hussin
    ;
    Mohd Nazrin Md Isa
    ;
    Basir M.S.S.M.
    Camellia cipher is another symmetric block cipher which allows the encryption and decryption process to share the same key. The cipher permits a 128-bits input data with three different key size: 128, 192 and 256 bits. This paper presents two hardware design approach of Camellia cipher, which are FPGA and custom-based design approach. These approaches utilized design softwares of Altera Quartus II with device family of Cyclone II and Synopsys Design Compiler. The performance of Camellia crypto-core design is then been evaluated based on the implementation platform in terms of speed, area and power. With an equal base of 50MHz of clock frequency, custom-based design is found more efficient than FPGA-based design due to the execution time achieved with 8.46ns, which is faster than the latter that consumed double the time with 16.075ns. The custom-based design achieved 15.13 Gbps of throughput. Besides, the power consumption of custom-based design is 1.3519 mW which is lower than the FPGA-based design. In a nutshell, the design has successfully done as it achieved expected encryption and decryption outcomes with acceptable performance.
  • Publication
    Design of multiplicative inverse value generator using logarithm method for AES algorithm
    ( 2020)
    Goh Yie Yen
    ;
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    Advanced Encryption Standard (AES) algorithm is one of the most widely used symmetric block cipher that is utilized in data protection through symmetric cryptography algorithm, as it offers high efficiency and ability in securing information. In AES, the SubByte/InvSubByte transformation costs an amount of memories for the lookup tables (LUT) that leads to area usage in hardware. As per mathematical equations, the SubByte/InvSubByte is able to share the same resource which is the multiplicative inverse value table. Instead of using LUTs, the multiplicative inverse values can be generated on-the-fly as needed. Therefore, this paper presents the custom hardware design and implementation of multiplicative inverse value generator using logarithm method specifically for AES algorithm. The logarithm method benefits the usage of antilog and log values in obtaining the multiplicative inverse value. The EDA tools as Intel Quartus Prime, Synopsys Design Compiler and IC Compiler are used to perform functional simulation, on synthesis analysis and block-level implementation. Detailed comparison is made between this work and previous implementation. The newly designed multiplicative inverse value generator has achieved the improvement on speed and area as compared to previous implementation. The area of the design is reduced around 8.5% with current improvement of 63.091 μm2, while the speed has increased to 2.54 ns with a positive slack of 0.11 ns, which is shorter than the previous implementation. The new design also outreached the performance of the common LUT-based design. © 2020 IEEE.
  • Publication
    Comparator design resistance mitigation by using Cadence Virtuoso tools in 45 nanometer process technology
    (IEEE, 2023-12)
    Michelle Ang Syn Yi
    ;
    Razaidi Hussin
    ;
    Fakhrul Zaman Rokhani
    This paper presents the resistance mitigation techniques for comparator design. Resistance plays an important role to semiconductor field. If resistance value higher than the design specification value, this might cause the electronic device burning and destroy. This project implements the techniques to mitigate resistance for the comparator design layout which are using multiple metal layers for routing, routing track improvement, increase metal width, increase number of vias and using higher metal layer for routing by using Cadence Virtuoso tools in 45 nanometer process technology. Based on the result, the total percentage for resistance mitigation for using multiple metal layers for routing is 73.66%, routing track improvement is 67.67%, increase metal width is 51.74%, increase number of vias is 50% and using higher metal layer for routing is 18.79%.
  • Publication
    Novel march WY approach for dynamic fault detection in memory BIST
    (IEEE, 2024-01)
    Wan Ying Loh
    ;
    Weng Fook Lee
    ;
    Razaidi Hussin
    ;
    Aiman Zakwan Jidin
    ;
    Norhawati Ahmad
    ;
    Nor Azura Zakaria
    Dynamic fault detection has shown an increasingly important role in the DPM level for embedded memories in SoC. Memory testing is directly related to the reliability of the whole SoC since embedded memories occupy a large area in the SoC and are used to store data for application usage. However, it is essential to bring down the test complexity of the March-based test algorithm for dynamic fault detection to maintain the test time and expenses within an acceptable economic range. March WY1 (66n) is proposed as the minimal March algorithm targeting unlinked two-operation single-cell dynamic faults and double-cell faults of types Sw and Saa to enhance the test efficiency for dynamic fault detection in SRAM. The proposed March WY1 (66n) has reduced test complexity by 4n compared to the well-known March MD2 (70n) while maintaining the same 100% dynamic fault coverages.
  • Publication
    Less memory and high accuracy logarithmic number system architecture for arithmetic operations
    ( 2021-09-01)
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    Interpolation is another important procedure for logarithmic number system (LNS) addition and subtraction. As a medium of approximation, the interpolation procedure has an urgent need to be enhanced to increase the accuracy of the operation results. Previously, most of the interpolation procedures utilized the first degree interpolators with special error correction procedure which aim to eliminate additional embedded multiplications. However, the interpolation procedure for this research was elevated up to a second degree interpolation. Proper design process, investigation, and analysis were done for these interpolation configurations in positive region by standardizing the same co-transformation procedure, which is the extended range, second order co-transformation. Newton divided differences turned out to be the best interpolator for second degree implementation of LNS addition and subtraction, with the best-achieved BTFP rate of +0.4514 and reduction of memory consumption compared to the same arithmetic used in european logarithmic microprocessor (ELM) up to 51%.
      21  1
  • Publication
    Design of Multiplicative Inverse Value Generator using Logarithm Method for AES Algorithm
    ( 2020-12-14)
    Yen, Goh Yie
    ;
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    Advanced Encryption Standard (AES) algorithm is one of the most widely used symmetric block cipher that is utilized in data protection through symmetric cryptography algorithm, as it offers high efficiency and ability in securing information. In AES, the SubByte/InvSubByte transformation costs an amount of memories for the lookup tables (LUT) that leads to area usage in hardware. As per mathematical equations, the SubByte/InvSubByte is able to share the same resource which is the multiplicative inverse value table. Instead of using LUTs, the multiplicative inverse values can be generated on-the-fly as needed. Therefore, this paper presents the custom hardware design and implementation of multiplicative inverse value generator using logarithm method specifically for AES algorithm. The logarithm method benefits the usage of antilog and log values in obtaining the multiplicative inverse value. The EDA tools as Intel Quartus Prime, Synopsys Design Compiler and IC Compiler are used to perform functional simulation, on synthesis analysis and block-level implementation. Detailed comparison is made between this work and previous implementation. The newly designed multiplicative inverse value generator has achieved the improvement on speed and area as compared to previous implementation. The area of the design is reduced around 8.5% with current improvement of 63.091 μm2, while the speed has increased to 2.54 ns with a positive slack of 0.11 ns, which is shorter than the previous implementation. The new design also outreached the performance of the common LUT-based design.
      18  3
  • Publication
    IoT Based Soil Nutrient Sensing System for Agriculture Application
    ( 2021-12-01)
    Othaman N.N.C.
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    ;
    Zakaria S.M.M.S.
    ;
    Isa M.M.
    Rice is the primary food source for millions of Asians and satisfies the most fundamental requirement for human survival. The paddy scarcity has heightened public awareness of the global food problem. Rice yield and quality are affected by various factors, including soil nutrients, irrigation, types of soil, and pests. This work proposed developing an Internet of Things (IoT) based mobile device for measuring soil nutrients in real-time. The proposed system consists of electrical conductivity (EC) and temperature sensors with TTGO T-Beam microcontroller and IoT connectivity. During experimental work, the results showed that the observed EC data near the calibration solution conductivity of 12.88mS/cm and 150mS/cm, which are less than 2% from the calibration solution's stated value. Furthermore, it is found that the measured EC value increases with temperature (linearly proportional). The study showed that the soil's EC of sensor node 1 at 5 cm depth without fertiliser is 1.04375mS/cm and with fertiliser is 3.86mS/cm, while at 10 cm depth without fertiliser is 0.65625mS/cm and with fertiliser is 420mS/cm. These investigations show that soil EC is directly linked to nutrient availability and soil depth.
      1  25
  • Publication
    An efficient modified booth multiplier architecture
    ( 2008)
    Razaidi Hussin
    Multiplier plays an important role in today’s compute intensive applications such as computer graphics and digital signal processing. This thesis described the design of an Efficient Modified Booth Multiplier Architecture. With the tradeoff between speed and area, the design of the Modified Booth Multiplier focused on high speed with a moderate increase in area. This was achieved by reducing the critical path delay in the basic element of the multiplier circuit. Multiplication is performed by generating the partial product of Modified Booth Encoding (MBE) and accumulating the entire partial product by an adder or compressor. The research began by examining the available encoding schemes used to generate the partial product and 4:2 compressor that are used to accumulate the partial product. The fastest MBE and the most efficient 4:2 compressor has been used to develop the multiplier. The multiplier performance was improved by adapting various methods such as Simplified Sign Extension (SSE) and a proper tree topology. The SSE method eliminated some counter or adders in a partial product row while the tree topology arrangement of the compressors and their interconnection accumulate the partial product. A Gajski’s rule had been used to evaluate the performance of the multiplier and the result shows that the new multiplier has reduced delays in producing the output. The new multiplier architecture has reduced delays to almost 2% to 7% compared to other multipliers. The high speed multiplier was then extended to develop a Floating Point (FP) multiplier. The FP multiplier had been successfully designed using Altera Quartus II software and implemented on MAX EPM7182SLC84-7 device. The result showed that the FP multiplier is 38% faster compared to conventional FP multiplier. In term of size, the FP multiplier is 26% bigger than conventional circuit. However the increase in area of the circuit can be tolerated since the aim was to enhance the speed of the FP Multiplier.
      2  5
  • Publication
    IoT Monitoring System for Fig in Greenhouse Plantation
    ( 2023-07-01)
    Mohd Firdaus Ibrahim
    ;
    Muammar Mohamad Isa
    ;
    Razaidi Hussin
    ;
    Syed Muhammad Mamduh Syed Zakaria
    ;
    Norhawati Ahmad
    ;
    Yuan C.K.J.
    ;
    Abdullah A.F.T.
    Fig is rich in nutrients and has a high market value due to its extensive application in promoting a nutritious food supply and supporting various medical disciplines. However, the equatorial climate in Malaysia poses significant difficulties for the large-scale cultivation of figs. Therefore, a Smart Monitoring System for controlled Greenhouse Plantation was proposed in this study to enable more efficient cultivation. The proposed system was equipped with LoRa and GSM to overcome the distance and data transmission limitations, developed using the Arduino Uno microcontroller. The proposed system consists of sensors to measure soil moisture, temperature, and humidity, while the data is transmitted using long-range LoRa communication to the control unit. The sensors circuit also has a solar power supply for convenient application in rural areas. The control unit is placed at a location with good data coverage. The system functioned well, and the monitoring parameter was accurately read, collected, and updated every 30 minutes. The optimal temperature, humidity, and soil moisture for growing fig is 22°C-33°C, > 60%, and 50%-60%, respectively. Real-time data monitoring enabled the sensors and control unit to achieve LoRa data transmission over a distance of 2.5 km. Any data exceeding the controlled parameters will trigger an alarm so that the user can perform corrective actions.
      2  22
  • Publication
    Area optimization of active reference band gap amplifier in cadence virtuoso
    ( 2024-02-08)
    Sheng T.W.
    ;
    Razaidi Hussin
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Siti Zarina Md Naziri
    ;
    Norhawati Ahmad
    ;
    Muammar Mohamad Isa
    ;
    Afzan Kamarudin
    Band Gap Amplifier is mostly used in integrated circuit (IC) chips. It is commonly used to generate temperature independent reference voltage. Band Gap Amplifier is essential and implemented widely in analog and digital circuits because it is temperature independent thus produces low voltage. In this work, layout of active reference band gap amplifier is designed in cadence virtuoso and the percentages of differences sizes of layouts are compared. The different versions of layout design are compared in the result to show the percentages of area optimization. The main layout designs such as layout 1 (without sharing source, drain and well), layout 2 (sharing source, drain without sharing wells), and layout 3 (share the source, drain, and well) are designed to get the comparison of area optimization. The results show that there is 27.73% reduction overall layout by applied several techniques to optimize the area in layout design in order to get a compactable layout.
      6  18