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  5. An efficient processing element architecture for pairwise sequence alignment
 
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An efficient processing element architecture for pairwise sequence alignment
Journal
2014 2nd International Conference on Electronic Design (ICED)
Date Issued
2014
Author(s)
Mohd Nazrin Md Isa
Universiti Malaysia Perlis
Sohiful Anuar Zainol Murad
Universiti Malaysia Perlis
Rizalafande Che Ismail
Universiti Malaysia Perlis
Muhammad Imran Ahmad
Universiti Malaysia Perlis
Asral Bahari Jambek
Universiti Malaysia Perlis
M. K. Md Kamil
Universiti Malaysia Perlis
DOI
10.1109/ICED.2014.7015850
File(s)
research repository notification.pdf (4.4 MB)
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