Phak Len Al Eh Kan
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Phak Len Al Eh Kan
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Phak, Len Al Eh Kan
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Ehkan, Phaklen
Kan, P. L.Eh
Ehkan, Phak Len
Ehkan, P. L.
Eh Kan, P.
Eh Kan, P.
Al Eh Kan, Phak Len
Eh Kan, Phaklen
Kan, P. Eh
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37005452000

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  • Publication
    Received signal strength indication (RSSI) code assessment for wireless sensors network (WSN) deployed Raspberry-Pi
    ( 2017-03-06)
    Mohd Ilman Jais
    ;
    Thennarasan Sabapathy
    ;
    Muzammil Jusoh
    ;
    Phak Len Al Eh Kan
    ;
    Murukesan L.
    ;
    Ismail I.
    ;
    R Badlishah Ahmad
    Wireless sensor network (WSN) is commonly used for localization applications. Through sniffing receive signal strength indicator (RSSI) in WSN system, localization and connection to access point highest RSSI can be done automatically. In this paper, we propose Raspberry-Pi (RasPi), based best access point selection method utilizing RSSI metric. The RasPi brings the advantages of a personal computer (PC) to the domain of sensor network, which makes it the perfect platform for interfacing with a wide variety of external peripherals. This work aims to investigate various source codes deployed on RasPi for localization purpose by sniffing the RSSI metric. Consequently, comparative analysis of its key elements and performances with some of the currently available wireless sensor nodes have shown that despite few disadvantages, RasPi remains an inexpensive single board computer (SBC) which has been used very successfully in sensor network domain and diverse range of research applications.
  • Publication
    Multipoint Relay Path for Efficient Topology Maintenance Algorithm in Optimized Link State Routing-Based for VANET
    ( 2024-01-01)
    Waleed Khalid Ahmed
    ;
    Mohd Nazri Mohd Warip
    ;
    Mohamed Elshaikh Elobaid Said Ahmed
    ;
    Phak Len Al Eh Kan
    The Optimal Link State Routing (OLSR) protocol employs multipoint relay (MPR) nodes to disseminate topology control (TC) messages, enabling network topology discovery and maintenance. However, this approach increases control overhead and leads to wasted network bandwidth in stable topology scenarios due to fixed flooding periods. To address these challenges, this paper presents an Efficient Topology Maintenance Algorithm (ETM-OLSR) for Enhanced Link-State Routing Protocols. By reducing the number of MPR nodes, TC message generation and forwarding frequency are minimized. Furthermore, the algorithm selects a smaller subset of TC messages based on the changes in the MPR selection set from the previous cycle, adapting to stable and fluctuating network conditions. Additionally, the sending cycle of TC messages is dynamically adjusted in response to network topology changes. Simulation results demonstrate that the ETM-OLSR algorithm effectively reduces network control overhead, minimizes end-to-end delay, and improves network throughput compared to traditional OLSR and HTR-OLSR algorithms.
  • Publication
    Implementation and analysis of GMM-based speaker identification on FPGA
    ( 2012)
    Phak Len Al Eh Kan
    The use of highly accurate identification systems is required in today’s society. Existing systems such as pin numbers and passwords can be forgotten or forged easily and they are no longer considered to offer a high level of security. The use of biological features (biometrics) is becoming widely accepted as the next level for security systems. One of the biometric is the human voice and it leads to the task of speaker identification. Speaker identification is the process of determining whether a speaker exists in a group of known speakers and identifying the speaker within the group. Speaker specific characteristics exist in speech signals due to different speakers having different resonances of the vocal tract. These differences can be exploited by extracting Mel-frequency Cepstral Coefficients (MFCCs) from the speech signal. A statistical modelling process known as Gaussian Mixture Model (GMM) is used to model the distribution of each speaker’s MFCCs in a multi-dimensional acoustic space. GMM involves with two phases called training and classification. The training phase is complex and is better suited for implementation in software. The classification phase is well suited for implementation in hardware and this allows for real time processing of multiple voice streams on large population sizes. Several innovative techniques are demonstrated which enable hardware system to obtain two orders of magnitude speed up over software while maintaining comparable levels of accuracy. A speedup factor of eighty six is achieved on hardware-based FPGA compared to a software implementation on a standard PC for this approach.
  • Publication
    A Fuzzy-Based Angle-of-Arrival Estimation System (AES) using Radiation Pattern Reconfigurable (RPR) antenna and modified gaussian membership function
    ( 2019)
    Mohd Ilman Jais
    ;
    Thennarasan Sabapathy
    ;
    Muzammil Jusoh
    ;
    R. Badlishah, Ahmad
    ;
    Mohd Haizal Jamaluddin
    ;
    Muhammad Ramlee Kamarudin
    ;
    Phak Len Al Eh Kan
    ;
    L. Murukesan Loganathan
    ;
    Soh Ping Jack
    Angle-of-arrival (AOA) estimation is an important factor in various wireless sensing applications, especially localization systems. This paper proposes a new type of AOA estimation sensor node, known as AOA-estimation system (AES) where the received signal strength indication (RSSI) from multiple radiation pattern reconfigurable (RPR) antennas are used to calculate the AOA. In the proposed framework, three sets of RPR antennas have been used to provide a coverage of 15 regions of radiation patterns at different angles. The salient feature of this RPR-based AOA estimation is the use of Fuzzy Inferences System (FIS) to further enhance the number of estimation points. The introduction of a modified FIS membership function (MF) based on Gaussian function resulted in an improved 85% FIS aggregation percentage between the fuzzy input and output. This later resulted in a low AOA error (of less than 5%) and root-mean- square error (of less than 8â—¦ ).
      1  17
  • Publication
    Deep Learning with FPGA: Age and Gender Recognition for Smart Advertisement Board
    ( 2023-10-06)
    Yeoh W.S.
    ;
    Fazrul Faiz Zakaria
    ;
    Mustapa M.
    ;
    Mohd Nazri Mohd Warip
    ;
    Phak Len Al Eh Kan
    ;
    Mozi A.M.
    Age and gender recognition are helpful in various applications, especially in the field of advertising. To replace the traditional advertising method that can only display the same contents to all audiences, a smart advertisement board capable of detecting age and gender of audiences to display relevant contents is required to increase the effectiveness of advertising. This paper will use two image datasets to train and test the Convolutional Neural Network (CNN) based architecture models for age and gender recognition using deep learning. The dataset that produced the best performing model will be implemented on three different devices to observe the performance of the models on each device. A gender recognition model with accuracy of 91.53% and age recognition model with accuracy of 59.62% is produced. The results have also shown the use of Field Programmable Gated Array (FPGA) has greatly boosted the performance of the models in terms of throughput and latency.
      1  14
  • Publication
    Breast cancer classification using deep learning and FPGA inferencing
    ( 2023-02-21)
    Wong E.H.
    ;
    Fazrul Faiz Zakaria
    ;
    Mustapa M.
    ;
    Mohd Nazri Mohd Warip
    ;
    Phak Len Al Eh Kan
    Implementing deep learning technology with FPGA as an accelerator has become a popular application due to its efficiency and performance. However, given the tremendous data generated on medical diagnosis, normal inference speed is not sufficient. Hence, the FPGA technology is implemented for fast inference. In this context, the FPGA accelerates the deep learning inference process for fast breast cancer classification with minimal latency on real-time deployment. This paper summarizes the findings of model deployment across various computing devices in deep learning technology with FPGA. The study includes model performance evaluation, throughput, and latency comparison with different batch sizes to the extent of expected delay for real-world deployment. The result concludes that FPGA is the most suitable to act as a deep learning inference accelerator with a high throughput-to-latency ratio and fast parallel inference.
      1
  • Publication
    Implementation of image file security using the advanced encryption standard method
    ( 2023-07-01)
    Ikhwan A.
    ;
    Rafikha Aliana A Raof
    ;
    Phak Len Al Eh Kan
    ;
    Yasmin Mohd Yacob
    ;
    Aslami N.
    The application of technology in this era has entered digitalization and is modern. Therefore, we are already in an era of advanced and rapid technological development. It has become a human need to exchange information in every activity. Documents that contain information that is frequently sought or used. The document's use also includes essential information. Document security is undoubtedly a significant factor in prioritizing important information in a document to prevent unauthorized people from misusing the document's vital information. Cryptography is a method of overcoming document security issues so that third parties cannot read the information or messages contained within the document. The 128-bit advanced encryption standard (AES) algorithm is one of the algorithms included in the cryptography technique. Additionally, it can be combined with operation modes such as electronic codebook (ECB) and cipher block chaining (CBC) to create an application that can generate random codes to improve the security of the data contained in the document.
      1
  • Publication
    Toward Adaptive and Scalable Topology in Distributed SDN Controller
    ( 2023-03-01)
    Kelian V.H.
    ;
    Mohd Nazri Mohd Warip
    ;
    R Badlishah Ahmad
    ;
    Phak Len Al Eh Kan
    ;
    Fazrul Faiz Zakaria
    ;
    Mohd Zaizu Ilyas
    The increasing need for automated networking platforms like the Internet of Things, as well as network services like cloud computing, big data applications, wireless networks, mobile Internet, and virtualization, has driven existing networks to their limitations. Software-defined network (SDN) is a new modern programmable network architectural technology that allows network administrators to control the entire network consistently and logically centralized in software-based controllers and network devices become just simple packet forwarding devices. The controller that is the network's brain, is mostly based on the OpenFlow protocol and has distinct characteristics that vary depending on the programming language. Its function is to control network traffic and increase network resource efficiency. Therefore, selecting the right controllers and monitoring their performance to increase resource usage and enhance network performance metrics is required. For network performance metrics analysis, the study proposes an implementation of SDN architecture utilizing an open-source OpenDaylight (ODL) distributed SDN controller. The proposed work evaluates the deployment of distributed SDN controller performance on three distinct customized network topologies based on SDN architecture for node-to-node performance metrics such as delay, throughput, packet loss, and bandwidth use. The experiments are conducted using the Mininet emulation tool. Wireshark is used to collect and analyse packets in real-time. The results obtained from the comparison of networks are presented to provide useful guidelines for SDN research and deployment initiatives.
      1
  • Publication
    Design and Implementation of Lifting Wavelet Transform Using Field Programmable Gate Arrays
    ( 2020-03-20)
    Taha T.B.
    ;
    Ruzelita Ngadiran
    ;
    Phak Len Al Eh Kan
    Lifting Wavelet transform (LWT) has an extensive usage in different image processing applications as image compression and information hiding. LWT is considered a good solution for hardware designs as it relies only on integer calculations while applying the wavelet transform. In this paper, an FPGA design and implementation of LWT is presented, the implementation is achieved using VHDL coding without importing off-shelf components which make the proposed design applicable to a wide range of devices. The design is based on parallel execution to perform LWT implementation with real time response. The design utilized 421 logic registers of DE2 Cyclone II (EP2C35F672C6) FPGA device with 151.91MHz frequency.
      2  20