Rizalafande Che Ismail
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Rizalafande Che Ismail
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Rizalafande, Che Ismail
Alternative Name
Ismail, Rizalafande C.
Rizalafande, Che Ismail
Chesmail, R.
Ismail, R. C.
Che Ismail, Rizalafande
Ismail, Rizalafande Che
Ismail, R. Che
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22634128600

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  • Publication
    Assessing Student Visual Fatigue in Virtual Semiconductor Labs via Head-Mounted Displays: A Computer Vision Syndrome Questionnaire (CVS-Q)
    ( 2023-01-01)
    Alnagrat A.J.A.
    ;
    Rizalafande Che Ismail
    ;
    Akeel A.A.A.
    ;
    Salem A.A.M.A.
    ;
    Khalefah S.E.A.S.
    ;
    Syed Zulkarnain Syed Idrus
    This paper evaluates visual fatigue among students in a virtual semiconductor lab using HMDs - the HP Reverb G2 and Oculus Quest 2 - and the CVS-Q questionnaire. The study measures the frequency of visual fatigue symptoms (never, occasionally, or always) and aims to determine the effects of HMD usage on visual fatigue and eye strain, providing insight into the benefits and drawbacks of using HMDs in virtual labs. The study was conducted during the COVID-19 pandemic and aims to determine the effects of HMD usage on visual fatigue and eye strain among students in a virtual semiconductor laboratory learning environment. The results of this evaluation will provide insight into the potential benefits and drawbacks of HMD usage in virtual laboratory environments and inform the development of strategies to mitigate visual fatigue.
  • Publication
    An Analysis of Interpolation Implementation for LNS Addition and Subtraction Function in Positive Region
    ( 2016)
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Ali Yeon Md Shakaff
    Interpolation is among of the most popular approach used in approximating the values in logarithmic number system (LNS) arithmetic design. This method that often combines with lookup tables (LUTs) manages to produce efficient LNS design in area, latency and accuracy. Current research proves that the combination of interpolators with co-transformation in LNS subtraction had shown extreme improvements in terms of speed and area, which is comparable to floating point (FLP) performance. Taking the advantage, this research had been conducted to analyze the implementation of these three interpolators, which are Taylor, Lagrange and modified Lagrange, in a 32-bit environment of the LNS addition and subtraction procedures with the first-order co-transformation in positive region. The designs were analyzed in two categories, which are the accuracy towards FLP and the total memory consumption. The best interpolator was selected based on the most optimum area consumption design with manageable accuracy in FLP limit. The outcome of this analysis could benefit further improvements in LNS design.
  • Publication
    An Evaluation of User Experience in a Virtual Semiconductor Laboratory Utilizing HMDs during Covid-19 Pandemic
    ( 2023-01-01)
    Alnagrat A.J.A.
    ;
    Mohamed A.S.I.
    ;
    Akeel A.A.A.
    ;
    Rizalafande Che Ismail
    ;
    Noureldeen A.M.I.
    ;
    Syed Zulkarnain Syed Idrus
    Virtual reality (VR) technology has been increasingly adopted for creating engaging educational environments, such as virtual laboratories. This study evaluated the user experience of a virtual semiconductor laboratory environment, utilizing Reverb G2 HMD VR headsets, through a user experience questionnaire (UEQ-S) and a psychometric analysis of its 26 items. Results showed that most participants found the virtual laboratories enjoyable, understandable, creative, easy to learn, and valuable. The psychometric analysis revealed relatively consistent and reliable construct related to user experience. The Kruskal-Wallis H test demonstrated that participants perceived the VR headsets to be easier to use when they found the virtual laboratories more enjoyable. However, there were no significant differences in user experience scores based on preferred VR headset, and user experience did not predict headset preference. These findings suggest that VR technology presents a promising solution for addressing practical challenges in education and fostering student engagement, although further research is needed to optimize the user experience and enhance student motivation.
  • Publication
    The impact of digitalisation strategy in higher education: technologies and new opportunities
    ( 2022-02)
    Ahmed Jamah Ahmed Alnagrat
    ;
    Rizalafande Che Ismail
    ;
    Syed Zulkarnain Syed Idrus
    ;
    Uonis Ali Imbayah Abukhatowah
    ;
    Valarmathie Gopalan
    Over the last 50 years, worldwide education has grown remarkably at all levels. Historically, these expanded education systems have never faced a greater challenge than COVID-19. The governments have forced the university to switch to online learning and virtual education overnights. As a result of COVID-19's disruptions to learning trajectories, institutions, lecturers, and students will continue to seek flexible ways to mitigate damage. The article incorporates a review of academic and policy literature concerning digitalisation and online learning in universities and how digitisation contributes to universities' development. The article outlines several useful strategies and steps to put into words how to develop a strategy for education during COVID-19. In this article, we explore processes, issues, and impacts of the rapid shift to digitalisation in higher education institutions (HEIs). The method has been used through online search in literature using bibliographic databases from the most relevant publications such as Scopusand Web of Science databases examined based on abstract and key words. This article discusses some of the ongoing issues that HEIs faced when they had to rapidly move their teaching online during the pandemic. For most HEIs and organisations across the globe, COVID-19 has accelerated the speed at which digitalisation and digital ways of working and service delivery include new ways of learning and working such as virtual reality (VR) technology. This has led to a recognition of the need for practically focused, effective inclusive digital interventions. The findings of this study indicate that policies and strategies are important for HEIs to overcome the COVID-19 challenges by using digital learning technology to plan and implement strategies for sustaining educational systems.
  • Publication
    Machine vision for laser defect in PV solar modules
    ( 2016)
    R. Shuaimi
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Sohiful Anuar Zainol Murad
    This paper presents a new methodology in inspection on laser scribe defect of PV thin film solar modules. The work focuses on the application of machine vision as an inspection tools which has successfully integrated in other manufacturing environment as pattern recognition utility. Compared to manual inspection by human, machine vision system could offer better measurement accuracy as scribe defects are extremely hard to detect due to their small sizes and complexity of the detection process. Studies were made to identify machine vision system screening capabilities to define different scribe defect by their inspection criteria. Current result with paper and broad samples indicates that the propose system can be used effectively to replace human evaluators that currently employs in manufacturing quality control. © 2016 IEEE.
  • Publication
    Enhancing fractal image compression speed using peer adjacent mapping with sum of absolute difference for computed radiography images
    ( 2020)
    N. A. Z. Rahman
    ;
    Rizalafande Che Ismail
    ;
    Ahmad Husni Mohd Shapri
    ;
    Mohd Nazrin Md Isa
    The encoding phase in full-search fractal image compression (FIC) is time-intensive as a sequential search must be performed through a massive domain pool to find the best-matched domain for each block of ranges. In this paper, a peer adjacent with the sum of absolute difference (SAD) mapping has been suggested to enhance the FIC speed while retaining the reconstructed image quality. The SAD similarity measure applied in searching the most matching domain between domain pool for a range before transformation in order to shorten the mapping process. Therefore, instead of performing a complete search in the next level, one requires to only search a close neighbourhood of the region computed from the previous search. The efficiency of the proposed method is evaluated using standard test image, SMPTE test pattern and standard computed radiography digital images from JSRT database, from which the peak signal-to-noise ratio (PSNR), compression time and compression ratio are calculated. The experimental results validate the effectiveness of the proposed method.
  • Publication
    A Novel Double Co-Transformation for a Simple and Memory Efficient Logarithmic Number System
    ( 2020-07-01)
    Basir M.S.S.M.
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    To date, co-transformation architecture is typically used in resolving the singularity issue in the logarithmic number system (LNS). The co-transformation was first introduced by Coleman, by using a rule of sign(r1) ≠ sign(r2) which translate the singularity into an argument that can be stored in two identical look-up tables (LUTs) with size of 2k. Recently, a portable 32-bit chipset preferred a small LUT, hitherto a co-transformation architecture is rearranged. This paper presents a novel double co-transformation, by means of first-order co-transformation architecture that covers-0.5 < r < 0 region is extended to r >-1 to replace the triumvirate F, D and E tables occupy by the interpolator. The accuracy settings at the co-transformation is compromised with the worst case error of 0.5 ulp. The outcome revealed a double co-transformation with Lagrange interpolator shows a decline in the total bit by 13% compared to European Logarithmic Microprocessor (ELM). With a simple architecture, the proposed double co-transformation is a promise for a fast LNS system.
  • Publication
    High performance Systolic array core architecture design for DNA sequencer
    ( 2018)
    Dayana Saiful Nurdin
    ;
    Mohd Nazrin Md Isa
    ;
    Rizalafande Che Ismail
    ;
    Muhammad Imran Ahmad
    This paper presents a high performance systolic array (SA) core architecture design for Deoxyribonucleic Acid (DNA) sequencer. The core implements the affine gap penalty score Smith-Waterman (SW) algorithm. This time-consuming local alignment algorithm guarantees optimal alignment between DNA sequences, but it requires quadratic computation time when performed on standard desktop computers. The use of linear SA decreases the time complexity from quadratic to linear. In addition, with the exponential growth of DNA databases, the SA architecture is used to overcome the timing issue. In this work, the SW algorithm has been captured using Verilog Hardware Description Language (HDL) and simulated using Xilinx ISIM simulator. The proposed design has been implemented in Xilinx Virtex -6 Field Programmable Gate Array (FPGA) and improved in the core area by 90% reduction.
      3  13
  • Publication
    Hardware Design of Combinational 128-bit Camellia Symmetric Cipher using 0.18µm Technology
    ( 2022)
    Chawalit Udom Sak
    ;
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    Camellia is another symmetric key block cipher with a 128-bit block size and key sizes of 128, 192, and 256 bits. As the hardware version of cipher implementation is getting popular, the Camellia hardware design should be constantly improved in terms of performance. The key aim of this research is to design and implement the improved version of Camellia cipher using custom-based approach based on 0.18µm technology. The new hardware Camellia design is synthesized using timing, area and power constraints to achieve less area, less power and high-speed design. Finally the results are been compared and analyzed with previous implementation in terms of performance parameters. The design is described using Verilog HDL and been verified using functional simulation from the Modelsim-Intel FPGA, while Synopsys had been utilized for synthesis process. Based on the generated synthesis reports, the total area consumed by the design on ASIC platform is 1294.11-unit area with a total cell area of 1176.25-unit area, while the total power consumption is 0.1245mW, and an increased speed of more than 80% as compared to previous design. In conclusion, this design had achieved better performance compared to previous design.
      3  17
  • Publication
    Design of multiplicative inverse value generator using logarithm method for AES algorithm
    ( 2020)
    Goh Yie Yen
    ;
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    Advanced Encryption Standard (AES) algorithm is one of the most widely used symmetric block cipher that is utilized in data protection through symmetric cryptography algorithm, as it offers high efficiency and ability in securing information. In AES, the SubByte/InvSubByte transformation costs an amount of memories for the lookup tables (LUT) that leads to area usage in hardware. As per mathematical equations, the SubByte/InvSubByte is able to share the same resource which is the multiplicative inverse value table. Instead of using LUTs, the multiplicative inverse values can be generated on-the-fly as needed. Therefore, this paper presents the custom hardware design and implementation of multiplicative inverse value generator using logarithm method specifically for AES algorithm. The logarithm method benefits the usage of antilog and log values in obtaining the multiplicative inverse value. The EDA tools as Intel Quartus Prime, Synopsys Design Compiler and IC Compiler are used to perform functional simulation, on synthesis analysis and block-level implementation. Detailed comparison is made between this work and previous implementation. The newly designed multiplicative inverse value generator has achieved the improvement on speed and area as compared to previous implementation. The area of the design is reduced around 8.5% with current improvement of 63.091 μm2, while the speed has increased to 2.54 ns with a positive slack of 0.11 ns, which is shorter than the previous implementation. The new design also outreached the performance of the common LUT-based design. © 2020 IEEE.
      32  2