Siti Zarina Md Naziri
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Siti Zarina Md Naziri
Official Name
Siti Zarina, Md Naziri
Alternative Name
Naziri, S. Z.M.
Naziri, S. Z. M.
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Scopus Author ID
26428387900

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  • Publication
    An Analysis of Interpolation Implementation for LNS Addition and Subtraction Function in Positive Region
    ( 2016)
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Ali Yeon Md Shakaff
    Interpolation is among of the most popular approach used in approximating the values in logarithmic number system (LNS) arithmetic design. This method that often combines with lookup tables (LUTs) manages to produce efficient LNS design in area, latency and accuracy. Current research proves that the combination of interpolators with co-transformation in LNS subtraction had shown extreme improvements in terms of speed and area, which is comparable to floating point (FLP) performance. Taking the advantage, this research had been conducted to analyze the implementation of these three interpolators, which are Taylor, Lagrange and modified Lagrange, in a 32-bit environment of the LNS addition and subtraction procedures with the first-order co-transformation in positive region. The designs were analyzed in two categories, which are the accuracy towards FLP and the total memory consumption. The best interpolator was selected based on the most optimum area consumption design with manageable accuracy in FLP limit. The outcome of this analysis could benefit further improvements in LNS design.
  • Publication
    Implementation of LNS addition and subtraction function with co-transformation in positive and negative region: A comparative analysis
    ( 2017-01-03)
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Ali Yeon Md Shakaff
    The European Logarithmic Microprocessor (ELM) had been an outstanding breakthrough in logarithmic number system (LNS) research history. The processor successfully reaches the par ability of floating-point (FLP) processor with its rapid and accurate design towards FLP. The design was able to improve the LNS addition and subtraction procedure, which are the drawbacks of any implementation of LNS arithmetic. ELM's subtraction operation had adopted a unique approach, which is the first-order co-transformation to overcome the singularity-to-zero issue of the non-linear function in negative region. Therefore, this research had been introduced to extensively compare and analyze the ELM-based addition and subtraction procedures with the same co-transformation technique implemented in positive region. In achieving this, two aspects are considered, which are the accuracy towards FLP and the memory consumption of both procedures in both regions. Conclusively, the exact ELM-based implementation in positive region of both operations could be realized and achieved comparable accuracy and memory area with a slight modification of the operation procedure. The outcome of this analysis could benefit further investigation of optimizing the LNS design for hardware implementation.
      1  25
  • Publication
    Implementation of LNS addition and subtraction function with co-transformation in positive and negative region: A comparative analysis
    ( 2016)
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Ali Yeon Md Shakaff
    The European Logarithmic Microprocessor (ELM) had been an outstanding breakthrough in logarithmic number system (LNS) research history. The processor successfully reaches the par ability of floating-point (FLP) processor with its rapid and accurate design towards FLP. The design was able to improve the LNS addition and subtraction procedure, which are the drawbacks of any implementation of LNS arithmetic. ELM's subtraction operation had adopted a unique approach, which is the first-order co-transformation to overcome the singularity-to-zero issue of the non-linear function in negative region. Therefore, this research had been introduced to extensively compare and analyze the ELM-based addition and subtraction procedures with the same co-transformation technique implemented in positive region. In achieving this, two aspects are considered, which are the accuracy towards FLP and the memory consumption of both procedures in both regions. Conclusively, the exact ELM-based implementation in positive region of both operations could be realized and achieved comparable accuracy and memory area with a slight modification of the operation procedure. The outcome of this analysis could benefit further investigation of optimizing the LNS design for hardware implementation.
      18  1
  • Publication
    Analysis of FXP adders and multipliers for speed- and area-efficient LNS arithmetic unit
    ( 2014)
    Rizalafande Che Ismail
    ;
    Siti Zarina Md Naziri
    ;
    Sohiful Anuar Zainol Murad
    ;
    J. N. Coleman
    This paper portrays the selection of hardware unit architectures to be implemented in the new LNS based on a 32bit system. The implementations of the LNS multiply and divide only require a FXP adder, while the LNS addition and subtraction function comprised of several memories, FXP adders and multipliers together with other supporting logics. Thus, in choosing the best FXP adders and multipliers, each of the arithmetic is functionally verified and synthesised using Synopsys Design Compiler in Faraday 0.18 μm CMOS technology based on a 32-bit system. Two types of performance measurement, which are the worst-case delay and the silicon area, are chosen as the evaluation arguments. From conducted analytical studies, the CLA/CSLA adder and Booth recoded with Wallace tree multiplier were the best FXP adder and multiplier blocks to be applied in the system since they were the fastest designs. Using these blocks, the synthesis of the LNS system produced an approximately 7.10 ns of critical delay for addition and subtraction, and solely 1.16 ns for multiplication and division. The total area for a complete LNS architecture was 599,871 μm2, in which 65% the size of previously designed LNS architecture of ELM. © 2014 IEEE.
      26  2
  • Publication
    Image processing for paddy disease detection using K-means clustering and GLCM algorithm
    ( 2021-12)
    A. F. A. Ahmad Effendi
    ;
    Mohd Nazrin Md Isa
    ;
    Muhammad Imran Ahmad
    ;
    Mohd Fikri Che Husin
    ;
    Siti Zarina Md Naziri
    The traditional human-based visual quality inspection approach in agriculture is unreliable and uneven due to various variables, including human errors. In addition to the lengthy processing durations, the traditional method necessitates plant disease diagnostic experts. On the other hand, existing image processing approaches in agriculture produce low-quality output images despite having a faster computation time. As a result, a more comprehensive set of image processing algorithms was used to improve plant disease detection. This research aims to develop an efficient method for detecting leaf diseases using image processing techniques. In this work, identifying paddy diseases based on their leaves involved a number of image-processing stages, including image pre-processing, image segmentation, feature extraction, and eventually paddy leaf disease classification. The proposed work targeted the segmentation step, whereby an input image is segmented using the K-Means clustering with image scaling and colour conversion technique in the pre-processing stage. In addition, the Gray Level Co-occurrence Matrix technique (GLCM) is used to extract the features of the segmented images, which are used to compare the images for classification. The experiment is implemented in MATLAB software and PC hardware to process infected paddy leaf images. Results have shown that K-Means Clustering and GLCM are capable without using the hybrid algorithm on each image processing phase and are suitable for paddy disease detection.
      1  74
  • Publication
    Design of multiplicative inverse value generator using logarithm method for AES algorithm
    ( 2020)
    Goh Yie Yen
    ;
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    Advanced Encryption Standard (AES) algorithm is one of the most widely used symmetric block cipher that is utilized in data protection through symmetric cryptography algorithm, as it offers high efficiency and ability in securing information. In AES, the SubByte/InvSubByte transformation costs an amount of memories for the lookup tables (LUT) that leads to area usage in hardware. As per mathematical equations, the SubByte/InvSubByte is able to share the same resource which is the multiplicative inverse value table. Instead of using LUTs, the multiplicative inverse values can be generated on-the-fly as needed. Therefore, this paper presents the custom hardware design and implementation of multiplicative inverse value generator using logarithm method specifically for AES algorithm. The logarithm method benefits the usage of antilog and log values in obtaining the multiplicative inverse value. The EDA tools as Intel Quartus Prime, Synopsys Design Compiler and IC Compiler are used to perform functional simulation, on synthesis analysis and block-level implementation. Detailed comparison is made between this work and previous implementation. The newly designed multiplicative inverse value generator has achieved the improvement on speed and area as compared to previous implementation. The area of the design is reduced around 8.5% with current improvement of 63.091 μm2, while the speed has increased to 2.54 ns with a positive slack of 0.11 ns, which is shorter than the previous implementation. The new design also outreached the performance of the common LUT-based design. © 2020 IEEE.
      34  3
  • Publication
    Image data compression using fast Fourier transform (FFT) technique for wireless sensor network
    ( 2024-02-08)
    Haron M.H.
    ;
    Mohd Nazrin Md Isa
    ;
    Muhammad Imran Ahmad
    ;
    Arshad M.A.M.
    ;
    Asral Bahari Jambek
    ;
    Siti Zarina Md Naziri
    ;
    Hussin R.
    ;
    Harun A.
    ;
    Rizalafande Che Ismail
    ;
    Shaiful Nizam Mohyar
    Agricultural settings present unique challenges for the transmission of huge amounts of images over long-range wireless networks. It is challenging to remotely gather data for transmission over a wireless network in research areas due to a lack of basic amenities like internet connections, especially in distant agricultural areas. In this research, the Fast Fourier Transform (FFT) method was used in conjunction with the Discrete Cosine Transform (DCT) method of image compression to achieve a higher compression ratio. In order for a Wireless Sensor Network (WSN) to provide compressed image data to a wireless based station, a LoRaWAN network has been identified. Low-power LoRaWAN networks may regularly transmit compressed images from an agricultural region to a monitoring system up to 15 km away. Images of golden apple snails were collected for this study from a variety of sources. The procedure was coded in MATLAB so that it could be run with input images being judged by the created algorithm. The input images can be compressed with a range of compression ratios (CR) from 3.00 to 50.00, as shown by the simulation results. Compressed image quality is measured not only by the above-mentioned criteria, but also by Mean Square Error (MSE) and Peak Signal to Noise Ratio (PSNR). According to the numbers, the best achievable compression ratio is 49.04, with an MSE of 172.72 and a PSNR of 25.75 at its highest.
      29  4
  • Publication
    Face Recognition and Identification using Deep Learning Approach
    ( 2021)
    KH Teoh
    ;
    Rizalafande Che Ismail
    ;
    Siti Zarina Md Naziri
    ;
    Razaidi Hussin
    ;
    Mohd Nazrin Md Isa
    ;
    Muhammad Sufyan Safwan Basir
    Human face is the significant characteristic to identify a person. Everyone has their own unique face even for twins. Thus, a face recognition and identification are required to distinguish each other. A face recognition system is the verification system to find a person’s identity through biometric method. Face recognition has become a popular method nowadays in many applications such as phone unlock system, criminal identification and even home security system. This system is more secure as it does not need any dependencies such as key and card but only facial image is needed. Generally, human recognition system involves 2 phases which are face detection and face identification. This paper describes the concept on how to design and develop a face recognition system through deep learning using OpenCV in python. Deep learning is an approach to perform the face recognition and seems to be an adequate method to carry out face recognition due to its high accuracy. Experimental results are provided to demonstrate the accuracy of the proposed face recognition system.
      2  21
  • Publication
    An Investigation of Extended Co-Transformation using Second-Degree Interpolation for Logarithmic Number System
    ( 2020)
    M. S. S. M. Basir
    ;
    Rizalafande Che Ismail
    ;
    Siti Zarina Md Naziri
    This paper addresses the proposal of improved logarithmic number system (LNS) with extended co-transformation and memory efficient second-degree Newton interpolator. Since the current interpolation with extension requires 4 look-up tables (LUTs), improvement is proposed to achieve requirement by employing only 3 LUTs with small silicon area. It was found that with the proposed extended co-transformation, a set of interpolation LUT that covered region-1 < r <-0.5 could be eliminated. Results from GNU simulator indicated that the maximum error for the proposed Newton interpolation was 9% lower compared to other current interpolators, although the total memory was unsatisfactory. An Implementation shows an efficient memory for a new LNS system, hence benefited for a dynamic real-time computation
      14  1
  • Publication
    Area optimization of active reference band gap amplifier in cadence virtuoso
    ( 2024-02-08)
    Sheng T.W.
    ;
    Razaidi Hussin
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Siti Zarina Md Naziri
    ;
    Norhawati Ahmad
    ;
    Muammar Mohamad Isa
    ;
    Afzan Kamarudin
    Band Gap Amplifier is mostly used in integrated circuit (IC) chips. It is commonly used to generate temperature independent reference voltage. Band Gap Amplifier is essential and implemented widely in analog and digital circuits because it is temperature independent thus produces low voltage. In this work, layout of active reference band gap amplifier is designed in cadence virtuoso and the percentages of differences sizes of layouts are compared. The different versions of layout design are compared in the result to show the percentages of area optimization. The main layout designs such as layout 1 (without sharing source, drain and well), layout 2 (sharing source, drain without sharing wells), and layout 3 (share the source, drain, and well) are designed to get the comparison of area optimization. The results show that there is 27.73% reduction overall layout by applied several techniques to optimize the area in layout design in order to get a compactable layout.
      6  35