Conference Publications
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PublicationDesign and simulation of Cylindrical Stacked Silicon Nanowire (SiNW) field-effect transistors(IEEE, 2023-12)In continuous effort to increase the current drive without sacrificing the off current and better off gate control on the channel, the MOSFET devices have advanced from classical, planar, single-gate and three-dimensional devices with multi-gate structures. Recently, multi-bridge-channel technology has become a feasible solution beyond FinFET multi-gate structure. In this work, we design Gate-All-Around (GAA) based on silicon nanowire. Numerical simulation based Silvaco Device tools has been used to design multiple number of cylindrical nanowires, then followed by different channel diameter, consisting of 20, 30 and 40 nm. The devices are the characterized on transconductance, threshold voltage, DIBL and subthreshold slope. The simulation results indicate that the device performance is best at a nanowire diameter of 20 nm due to improved gate control over charge distribution. Regarding the number of nanowires, the voltage performance is not significantly affected by Nnw =1 or higher. However, higher numbers of nanowires, such as Nnw = 3, demonstrate improved drain current and transconductance.
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PublicationNovel march WY approach for dynamic fault detection in memory BIST(IEEE, 2024-01)Dynamic fault detection has shown an increasingly important role in the DPM level for embedded memories in SoC. Memory testing is directly related to the reliability of the whole SoC since embedded memories occupy a large area in the SoC and are used to store data for application usage. However, it is essential to bring down the test complexity of the March-based test algorithm for dynamic fault detection to maintain the test time and expenses within an acceptable economic range. March WY1 (66n) is proposed as the minimal March algorithm targeting unlinked two-operation single-cell dynamic faults and double-cell faults of types Sw and Saa to enhance the test efficiency for dynamic fault detection in SRAM. The proposed March WY1 (66n) has reduced test complexity by 4n compared to the well-known March MD2 (70n) while maintaining the same 100% dynamic fault coverages.
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PublicationA proposed framework for improving the detection and classification of Ki67 expression in Astrocytoma histopathological images(IEEE, 2024-03)Detecting and classifying the Ki67 expression is a challenging process. The inconsistency in staining intensity and the variations in image quality are the main factors that may reduce the performance of an automated system. Therefore, this study proposes a framework that objectively improves detecting and classifying Ki67 expression in astrocytoma histopathological images. The proposed framework began with implementing the double stain normalization procedure to reduce the colour-staining intensity variations. Then, the system automatically enhanced the morphological features of the Ki67 expression. The following step was to segment the enhanced images by using the U-Net network model. The last step of the proposed framework was to localize and classify the Ki67 expression based on the modified YOLOv3 model. In conclusion, the proposed YOLOv3 model produced a high detection result with a mean average precision of 0.80 for detecting Ki67-positive cells and 0.87 for detecting Ki67-negative cells.
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PublicationComparator design resistance mitigation by using Cadence Virtuoso tools in 45 nanometer process technology(IEEE, 2023-12)This paper presents the resistance mitigation techniques for comparator design. Resistance plays an important role to semiconductor field. If resistance value higher than the design specification value, this might cause the electronic device burning and destroy. This project implements the techniques to mitigate resistance for the comparator design layout which are using multiple metal layers for routing, routing track improvement, increase metal width, increase number of vias and using higher metal layer for routing by using Cadence Virtuoso tools in 45 nanometer process technology. Based on the result, the total percentage for resistance mitigation for using multiple metal layers for routing is 73.66%, routing track improvement is 67.67%, increase metal width is 51.74%, increase number of vias is 50% and using higher metal layer for routing is 18.79%.
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PublicationThe design evolution of trio-band vivaldi antenna with meander-line-fed shape for ground penetrating radar application(IEEE, 2024-01)This paper is proposed based on considerable reviewed design techniques. It works at 200MHz, 800MHz and 1,200MHz named as “Trio-Band” with the fixed size of 300mm×300mm×1.6mm of the FR4 substrate. The antenna application is for Ground Penetrating Radar (GPR) with targeted depth range is from 10cm to 1,000cm. The combination of slotted shapes which is Half-circle, Staircase, Quarter-eclipse and Circular-Ring are applied to achieve the Trio-Band with the parametric analysis to determine the appropriate size. The final Vivaldi antenna achieves the reflective coefficient (S11) with -30.05dB (200MHz), -12.05dB (800MHz) and -15.35dB (1,200MHz) as well as 50Ω of impedance matching.