Zaliman Sauli
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Preferred name
Zaliman Sauli
Official Name
Zaliman, Sauli
Alternative Name
Sauli, Zaliman B.
Sauli, Zaliman
Sauli, Z.
Main Affiliation
Scopus Author ID
24554644300
Researcher ID
FWC-2779-2022

Research Output

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  • Publication
    Investigation of the absorption coefficient, refractive index, energy band gap, and film thickness for Al0.11Ga0.89N, Al0.03Ga0.97N, and GaN by optical transmission method
    ( 2009-07)
    Naser M. Ahmed
    ;
    Zaliman Sauli
    ;
    Uda Hashim
    ;
    Yarub Al-Douri
    The design of optoelectronic devices fabricated from III-Nitride materials is aided by knowledge of refractive index and absorption coefficient of these materials .The optical properties of Al0.11Ga0.89N, Al0.03Ga0.97N, and GaN grown by MOVPE on sapphire were investigated by means of transmittance measurements .The optical transmission method is successfully used to determine the refractive index (n), absorption coefficient (α), film thickness and energy gap of three samples of film over the spectral range of (1-5 eV)
  • Publication
    Simulation and investigation of Si-based piezoelectric micromachined ultrasonic transducer (PMUT) performances
    ( 2023-07)
    Hasnizah Aris
    ;
    Muhammad Nizam Bin Rosli
    ;
    Mohammad Nuzaihan Md Nor
    ;
    Zaliman Sauli
    ;
    Wan Mokhdzani Wan Nor Haimi
    Micro-electromechanical system (MEMS) based piezoelectric ultrasonic transducers for acoustic imaging of the surroundings are known as piezoelectric micromachined ultrasonic transducers (PMUTs). This research proposes a structural design of the PMUT with four fixed-guided beams. The beam is subjected to lateral loads, with vectors that are perpendicular to the longitudinal axis. This project simulated Piezoelectric Micromachined Ultrasonic Transducer (PMUT) with three different material properties i.e. Aluminium Nitride (AlN), Lead zirconate titanate (PZT) and Zinc Oxide (ZnO). Based on the study, it was found that reducing the beam dimensions and increasing the plate size will result in the first mode frequency reduction from 1.33x107 Hz to 3.74x106 Hz. Other than that, it was found that AlN PMUT experienced the maximum deflection of 6.3413 to 6.3478 μm when the loads applied in the range of 50 to 200 μN/m2. When the piezoelectric material changed to PZT, we obtained the maximum deflections of 0.3771 to 0.3786 μm when the same loads range applied to the PMUT. As for the ZnO PMUT, the maximum deflections obtained were in between 0.1702 μm to 0.1772 μm with the loads are maintained as in the loads applied to the AlN and PZT. This study proved the significant impact of altering the structural dimensions and material properties of PMUTs on their operational characteristics, specifically the first mode frequency and deflection behavior.
  • Publication
    A 12 GHz LC-VCO Implemented with S’ shape Inductor using silicon-on sapphire substrate
    ( 2022-12)
    Nazuhusna Khalid
    ;
    Aimi Noorliyana Hashim
    ;
    Nurul Izza Mohd Nor
    ;
    Shahrir Rizal Kasjoo
    ;
    Zaliman Sauli
    ;
    Mohd Norhafiz Hashim
    ;
    M.S Mispan
    A voltage-controlled oscillator (VCO) is an electronic oscillator whose oscillation frequency is controlled by a voltage input. In a VCO, low-phase noise while consuming less power is preferred. The tuning gain and noise in the control signal produce phase noise; more noise or tuning gain implies more phase noise. Sources of flicker noise (1/f noise) in the circuit, the output power level, and the loaded Q factor of the resonator are all crucial factors that influence phase noise. As a result, creating a resonator with a high Q-factor is essential for improving VCO performance. As a result, this paper describes a 12 GHz LC Voltage- Controlled Oscillator (VCO) employed with a ‘S’ shape inductor to improve phase noise and power performance. The phase noise for the VCO was reduced using a noise filtering technique. To reduce substrate loss and improve the Q factor, the inductor was designed on a high-resistivity Silicon-on Sapphire (SOS) substrate. At 12 GHz, the optimised S’ shape inductor has the highest Q-factor of 50.217. At 10 MHz and 100 MHz, the phase noise of the 12 GHz LC-VCO was -131.33 dBc/Hz and -156.71 dBc/Hz, respectively. With a 3.3 V power supply, the VCO core consumes 26.96 mW of power. Based on the findings, it is concluded that using an ‘S’ shape inductor in the VCO circuit will enable the development of low-cost, high-performance, very low-power system-on-chip wireless transceivers with longer battery life.
  • Publication
    A 1.5 V, 0.85-13.35 GHZ MMIC low noise amplifier design using optimization technique
    ( 2009)
    Arjuna Marzuki
    ;
    Ali Yeon Md Shakaff
    ;
    Zaliman Sauli
    This paper describes how a broadband, 1.5 V, 0.85-13.35 GHz low noise amplifier in 0.15 μm 85 GHz PHEMT process is synthesized to simultaneously meet multiple design specifications such as bandwidth, noise figure, power gain and power consumption. Power-constrained synthesis technique is used to design the broadband amplifier. The simulated peak S21 is 19.8 dB, maximum noise Figure is 2.5 dB, 3-dB bandwidth is 12.5 GHz and power consumption is 73.5 mW. The calculated Figure of merit (FOM) is better than many reported broadband low noise amplifier (LNA).
  • Publication
    Heat dissipation analysis under natural convection condition on high power LED
    ( 2013)
    Rajendaran Vairavan
    ;
    Zaliman Sauli
    ;
    Vithyacharan Retnasamy,
    ;
    Kamarudin Hussin
    As the technology downscales with superior power and increased package density, the thermal effects of the high power LED are significant. Thus, the operating junction temperature of the high power light emitting diodes has to be reduced. In this paper, evaluation on single chip high power light emitting was done. The prime motive of this work was to assess the effect of heat slug size on the junction temperature and stress of LED chip under natural convection condition at ambient temperature of 25°C. Two sizes of rectangular heat slug were used. Simulation was carried out using Ansys version 11. Input power of 0.1W and 1W was applied to LED. Simulated results indicated that a larger slug size is favorable for a lower operating junction temperature and stress of the LED chip.
  • Publication
    FSS microchannel fluid flow profile investigation at high and low Re number
    ( 2013)
    Nor Shakirina Nadzri
    ;
    Vithyacharan Retnasamy
    ;
    Zaliman Sauli
    ;
    Tan Hsio Mei
    ;
    Kamarudin Hussin
    The fundamental understanding of dynamic fluid flow behavior in different geometry channel is crucial due to transport phenomena influence on the key design and process control of the microfluidic systems. Recently, the Computational Fluid Dynamics (CFD) technology has received priority to fully understand the performance of the microfluidic design. In this paper, simulation of liquid flow over forward facing step (FFS) microchannel has been explored using CFD-Ansys software. This work focused on velocity profiles for low and high Reynolds (Re) numbers. Different step heights were used as main parameter. The results revealed a parabolic profile across the x-axis channel. Besides that, recirculation zone is detected near the step for Re=500. An increase for step height value contributed to higher fluid flow velocity.
  • Publication
    High power LED heat dissipation analysis via copper diamond slug
    ( 2013)
    Rajendaran Vairavan
    ;
    Zaliman Sauli
    ;
    Vithyacharan Retnasamy
    ;
    Kamarudin Hussin
    The emergence of high power light emitting diode as a novel electronic based light source is due to its vast advantage in terms of optical efficacy, low power consumption and enhanced life time. However, the performances of the LEDs are dependent on the junction temperature as it is inherited high heat production. Hence, proper evaluation of the junction temperature is very significant. In this paper, the heat dissipation of single chip high power LED attached to copper diamond based cylindrical heat slug was scrutinized through simulation. The heat dissipation was characterized in terms of junction temperature. In addition, the stress of the LED chip is evaluated with varied input power. Ansys version 11 was used for the simulation. The simulated results reveal that at input power of 1 W, the max junction temperature of the LED is 114.69°C.
  • Publication
    Interrogation of surface roughness and bond force effect
    ( 2013)
    Zaliman Sauli
    In the macro world surface roughness is a feature undoubtedly not to be ignored. In the current trend towards the nano-scale feature in the devices related to the semiconductor and other various niche, surface roughness is being propelled as an important element. In this work the surface roughness at nano level is investigated for the adhesion interaction and influence. The samples for the roughness feature and ranges were prepared using controlled plasma etching. The wire bonding bond force parameter was chosen as the factor to be tested and shear test as the response. The shear value ranged from 13g to 22g for the low to high bond force respectively for the lower range surface roughness, for the higher surface roughness the value ranged 5g to 9g respectively. The interaction shows surface roughness has tangible effect on adhesion for a more thorough detailed investigation.
  • Publication
    Design and analysis of wideband ladder-type film bulk acoustic wave resonator filters in Ku-Band
    ( 2013-06)
    Nurul Izza Mohd Nor
    ;
    Kriang Shah
    ;
    Jugdutt Singh
    ;
    Zaliman Sauli
    This paper presents the design of ladder-type filters based on film bulk acoustic wave resonator (FBAR) in Ku-band. The proposed FBAR filter has an insertion loss of −3 dB, out-of-band rejection of −12 dB and 3 dB bandwidth of 1.0 GHz from 15 GHz to 16 GHz. Based on the characteristics of the FBAR filter, the expected characteristics of FBAR resonators are determined by using the 1D numerical analysis. This design proves that it is possible to design a wide-bandwidth FBAR filter in Ku-band.
  • Publication
    Failure analysis on silicon semiconductor device materials: optical and high-resolution microscopic assessments
    ( 2022)
    Subash Chandra Bose Gopinath
    ;
    Santheraleka Ramanathan
    ;
    Mohd Najib Mohd Yasin
    ;
    Mohd Ibrahim Shapiai Razak
    ;
    Zool Hilmi Ismail
    ;
    Syahrizal Salleh
    ;
    Zaliman Sauli
    ;
    Sreeramanan Subramaniam
    ;
    M.B. Malarvili
    Defects of silicon (Si) semiconductor epilayers are crucial to be identified at laboratory environs. The identification of failure and its rectification at laboratory settings is essential for large-scaling manufacturing of narrowed down semiconductor devices. This research documented the inspection, identification and the solution for defects found in the Si semiconductor epilayers, fabricated by a simple and conventional photolithography technique, with the integration of metal oxide nanomaterial, zinc oxide (ZnO). The semiconductor epilayers, Si wafer, Si oxide and ZnO coated SiO2 layer were formed and examined. Optical microscope images [high power microscope (HPM) and 3D profilometer] reveal smooth surface of semiconductor epilayers development through thermal oxidation and photolithography techniques. High power ultraviolet-visible (UV-Vis) justified the accuracy of wet thermal oxidation by examining the thickness of oxide layer on Si wafer at 3837.3 Ã…. The X-ray diffraction (XRD) analysis of sol-gel synthesized ZnO affirmed the hexagonal crystalline state and its nanoscale size at 54 nm. Field emission scanning electron microscopy (FESEM) has shown the insight of Si epilayer morphology with its elemental composition, which provides details of foreign substances on semiconductor surface. ZnO deposited Si epilayer was prepared through lamella preparation, prior to the cross-sectional field emission transmission electron microscopy (FETEM) analysis of the semiconductor, which revealed the uniformity of fabrication and ZnO distribution at Si epilayer. Failure analysis reported several defects on the Si epilayers in the state of patches and accumulation of impurities. The potential cause of the defects and the respective solutions are discussed as the accuracy and handling must be ensured throughout the fabrication process, to develop a flawless semiconductor for high performance applications.