Afzan Kamarudin
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Afzan Kamarudin
Official Name
Afzan, Kamarudin
Alternative Name
Kamarudin, Afzan A.A.
Kamarudin, Afzan
Kamarudin, A.
Kamarudin, A. A.A.
Main Affiliation
Scopus Author ID
22635093800
Researcher ID
FCZ-7188-2022

Research Output

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  • Publication
    Design and Analysis of 32-Bit Signed and Unsigned Multiplier Using Booth, Vedic and Wallace Architecture
    ( 2021-03-01)
    Yong K.M.
    ;
    Razaidi Hussin
    ;
    Afzan Kamarudin
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Siti Zarina Md Naziri
    This paper presents the implementation and performance comparison of the Booth encoding technique and Wallace Tree reduction scheme on Vedic architecture. The radix-4 Booth encoder is widely used to enhance the multiplication speed as it has the capability to reduce the number of partial products generated by half. Vedic multiplier partitions the inputs into two blocks to speed up the partial product generation and Wallace Tree reduction scheme speed up the partial product addition process by eliminating the carry chain of the addition. Radix-4 Booth encoding scheme Vedic multiplier with and without Wallace Tree partial product reduction scheme for signed and unsigned multiplication was designed and synthesized in Synopsys 130 nm technology. For unsigned multiplier, the Booth-Vedic multiplier is 37.29% faster and 26.13% smaller while the Booth-Vedic-Wallace multiplier is 39.79% faster and 28.81% smaller when compared with Vedic multiplier. The performance of both multipliers was dropped when used in signed multiplication due to signed extension during the partial product addition process. All the multiplier is functionally verified using modified testbench that is based on the concept of UVM testbench.
  • Publication
    "look & blink" two step verification security log in system
    ( 2021-03-01)
    Kai Qi L.
    ;
    Razaidi Hussin
    ;
    Afzan Kamarudin
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Naziri S.Z.M.
    A new artificial intelligence security design which is face recognition with eye blinking login system is proposed. It aims to strengthen the security account for each user using artificial intelligence technology and increase speed and user convenience for security during login. The face of a person cannot be copied and it can replace the username of the user, while eye blinking detection is another step for double verification replacing the password of a user. It is a two-step verification process that can be applied to all sorts of account login field so that this technology can replace the old school username with a password security system. The recognition system used a real-time where it is reducing the number of hackers in the field as it is impossible to hack a person's real-time face. The proposed system has been tested and analyzed the functionality by accessing the personal account in the university's portal.
  • Publication
    Development of fruits artificial intelligence segregation
    ( 2021-12)
    Norhidayah Mohd Rozi
    ;
    Razaidi Hussin
    ;
    Muammar Mohamad Isa
    ;
    Syed Muhammad Mamduh Syed Zakaria
    ;
    Afzan Kamarudin
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Siti Zarina Md Naziri
    Higher output was needed as technology advance to meet human needs and industry demands. Fruits Artificial Intelligence Segregation (FAIS) is a project that uses image processing to detect and differentiate between various types of fruits. This paper proposes an OpenCV python, and the Convolution Neural Network (CNN) is used to complete the segregation of multiple fruits. The code extracts the fruit's characteristics and separates them based on their color and shape once placed in front of the camera to implement liveness detection. This paper shows the accuracy and reliability of the Fruits Artificial Intelligence Segregation (FAIS) system based on the number of datasets.
      2  10
  • Publication
    Area optimization of active reference band gap amplifier in cadence virtuoso
    ( 2024-02-08)
    Sheng T.W.
    ;
    Razaidi Hussin
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Siti Zarina Md Naziri
    ;
    Norhawati Ahmad
    ;
    Muammar Mohamad Isa
    ;
    Afzan Kamarudin
    Band Gap Amplifier is mostly used in integrated circuit (IC) chips. It is commonly used to generate temperature independent reference voltage. Band Gap Amplifier is essential and implemented widely in analog and digital circuits because it is temperature independent thus produces low voltage. In this work, layout of active reference band gap amplifier is designed in cadence virtuoso and the percentages of differences sizes of layouts are compared. The different versions of layout design are compared in the result to show the percentages of area optimization. The main layout designs such as layout 1 (without sharing source, drain and well), layout 2 (sharing source, drain without sharing wells), and layout 3 (share the source, drain, and well) are designed to get the comparison of area optimization. The results show that there is 27.73% reduction overall layout by applied several techniques to optimize the area in layout design in order to get a compactable layout.
      1