Razaidi Hussin
Thumbnail Image
Preferred name
Razaidi Hussin
Official Name
Razaidi, Hussin
Alternative Name
Hussin, R.
Razaidi, Hussin
Hussin, Razaidi Bin
Hussin, Razaidi
Razaidi, H.
Main Affiliation
Scopus Author ID
22634137400
Researcher ID
AAU-6856-2020

Research Output

Filters

2
19
Reset filters

Settings
Now showing 1 - 10 of 19
  • Publication
    Comparator design resistance mitigation by using Cadence Virtuoso tools in 45 nanometer process technology
    (IEEE, 2023-12)
    Michelle Ang Syn Yi
    ;
    Razaidi Hussin
    ;
    Fakhrul Zaman Rokhani
    This paper presents the resistance mitigation techniques for comparator design. Resistance plays an important role to semiconductor field. If resistance value higher than the design specification value, this might cause the electronic device burning and destroy. This project implements the techniques to mitigate resistance for the comparator design layout which are using multiple metal layers for routing, routing track improvement, increase metal width, increase number of vias and using higher metal layer for routing by using Cadence Virtuoso tools in 45 nanometer process technology. Based on the result, the total percentage for resistance mitigation for using multiple metal layers for routing is 73.66%, routing track improvement is 67.67%, increase metal width is 51.74%, increase number of vias is 50% and using higher metal layer for routing is 18.79%.
  • Publication
    Novel march WY approach for dynamic fault detection in memory BIST
    (IEEE, 2024-01)
    Wan Ying Loh
    ;
    Weng Fook Lee
    ;
    Razaidi Hussin
    ;
    Aiman Zakwan Jidin
    ;
    Norhawati Ahmad
    ;
    Nor Azura Zakaria
    Dynamic fault detection has shown an increasingly important role in the DPM level for embedded memories in SoC. Memory testing is directly related to the reliability of the whole SoC since embedded memories occupy a large area in the SoC and are used to store data for application usage. However, it is essential to bring down the test complexity of the March-based test algorithm for dynamic fault detection to maintain the test time and expenses within an acceptable economic range. March WY1 (66n) is proposed as the minimal March algorithm targeting unlinked two-operation single-cell dynamic faults and double-cell faults of types Sw and Saa to enhance the test efficiency for dynamic fault detection in SRAM. The proposed March WY1 (66n) has reduced test complexity by 4n compared to the well-known March MD2 (70n) while maintaining the same 100% dynamic fault coverages.
  • Publication
    A new 13N-complexity memory built-in self-test algorithm to balance static random access memory static fault coverage and test time
    (Institute of Advanced Engineering and Science, 2025-02)
    Aiman Zakwan Jidin
    ;
    Razaidi Hussin
    ;
    Mohd Syafiq Mispan
    ;
    Lee Weng Fook
    As memories dominate the system-on-chip (SoC), their quality significantly impacts the chip manufacturing yield. There is a growing need to reduce the chip production time and cost, which mainly depends on the testing phase. Hence, a memory built-in self-test (MBIST) utilizing a low-complexity, high-fault-coverage test algorithm is essential for efficient and thorough memory testing. The March AZ1 algorithm, with 13N complexity, was created earlier to balance the test length and fault coverage. However, poor positioning of a write operation in its test sequence caused the reduction of the transition coupling fault (CFtr) detection. This paper presents the creation of the March AZ algorithm, modified from the March AZ1 algorithm, to increase CFtr coverage while preserving the same complexity. It was accomplished by analyzing the fault coverage offered by the March AZ1 algorithm and then reorganizing its test sequence to address the limitation in detecting CFtr. The newly produced March AZ1 algorithm was successfully implemented in an MBIST controller. The simulation tests validated its functionality and demonstrated that the CFtr coverage was enhanced from 62.5% to 75%, achieving an overall fault coverage of 83.3%. Therefore, with 13N complexity, it offers the best fault coverage among all the existing test algorithms with a complexity below 18N.
  • Publication
    "Look & Blink" two step verification security log in system
    ( 2021-03-01)
    Kai Qi L.
    ;
    Razaidi Hussin
    ;
    Afzan Kamarudin
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Naziri S.Z.M.
    A new artificial intelligence security design which is face recognition with eye blinking login system is proposed. It aims to strengthen the security account for each user using artificial intelligence technology and increase speed and user convenience for security during login. The face of a person cannot be copied and it can replace the username of the user, while eye blinking detection is another step for double verification replacing the password of a user. It is a two-step verification process that can be applied to all sorts of account login field so that this technology can replace the old school username with a password security system. The recognition system used a real-time where it is reducing the number of hackers in the field as it is impossible to hack a person's real-time face. The proposed system has been tested and analyzed the functionality by accessing the personal account in the university's portal.
      2  38
  • Publication
    Design of multiplicative inverse value generator using logarithm method for AES algorithm
    ( 2020)
    Goh Yie Yen
    ;
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    Advanced Encryption Standard (AES) algorithm is one of the most widely used symmetric block cipher that is utilized in data protection through symmetric cryptography algorithm, as it offers high efficiency and ability in securing information. In AES, the SubByte/InvSubByte transformation costs an amount of memories for the lookup tables (LUT) that leads to area usage in hardware. As per mathematical equations, the SubByte/InvSubByte is able to share the same resource which is the multiplicative inverse value table. Instead of using LUTs, the multiplicative inverse values can be generated on-the-fly as needed. Therefore, this paper presents the custom hardware design and implementation of multiplicative inverse value generator using logarithm method specifically for AES algorithm. The logarithm method benefits the usage of antilog and log values in obtaining the multiplicative inverse value. The EDA tools as Intel Quartus Prime, Synopsys Design Compiler and IC Compiler are used to perform functional simulation, on synthesis analysis and block-level implementation. Detailed comparison is made between this work and previous implementation. The newly designed multiplicative inverse value generator has achieved the improvement on speed and area as compared to previous implementation. The area of the design is reduced around 8.5% with current improvement of 63.091 μm2, while the speed has increased to 2.54 ns with a positive slack of 0.11 ns, which is shorter than the previous implementation. The new design also outreached the performance of the common LUT-based design. © 2020 IEEE.
      34  3
  • Publication
    Face Recognition and Identification using Deep Learning Approach
    ( 2021)
    KH Teoh
    ;
    Rizalafande Che Ismail
    ;
    Siti Zarina Md Naziri
    ;
    Razaidi Hussin
    ;
    Mohd Nazrin Md Isa
    ;
    Muhammad Sufyan Safwan Basir
    Human face is the significant characteristic to identify a person. Everyone has their own unique face even for twins. Thus, a face recognition and identification are required to distinguish each other. A face recognition system is the verification system to find a person’s identity through biometric method. Face recognition has become a popular method nowadays in many applications such as phone unlock system, criminal identification and even home security system. This system is more secure as it does not need any dependencies such as key and card but only facial image is needed. Generally, human recognition system involves 2 phases which are face detection and face identification. This paper describes the concept on how to design and develop a face recognition system through deep learning using OpenCV in python. Deep learning is an approach to perform the face recognition and seems to be an adequate method to carry out face recognition due to its high accuracy. Experimental results are provided to demonstrate the accuracy of the proposed face recognition system.
      2  21
  • Publication
    Area optimization of active reference band gap amplifier in cadence virtuoso
    ( 2024-02-08)
    Sheng T.W.
    ;
    Razaidi Hussin
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Siti Zarina Md Naziri
    ;
    Norhawati Ahmad
    ;
    Muammar Mohamad Isa
    ;
    Afzan Kamarudin
    Band Gap Amplifier is mostly used in integrated circuit (IC) chips. It is commonly used to generate temperature independent reference voltage. Band Gap Amplifier is essential and implemented widely in analog and digital circuits because it is temperature independent thus produces low voltage. In this work, layout of active reference band gap amplifier is designed in cadence virtuoso and the percentages of differences sizes of layouts are compared. The different versions of layout design are compared in the result to show the percentages of area optimization. The main layout designs such as layout 1 (without sharing source, drain and well), layout 2 (sharing source, drain without sharing wells), and layout 3 (share the source, drain, and well) are designed to get the comparison of area optimization. The results show that there is 27.73% reduction overall layout by applied several techniques to optimize the area in layout design in order to get a compactable layout.
      6  35
  • Publication
    Hardware Design of Combinational 128-bit Camellia Symmetric Cipher using 0.18μm Technology
    (Institute of Electrical and Electronics Engineers Inc., 2022-01-01)
    Sak C.U.
    ;
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    Camellia is another symmetric key block cipher with a 128-bit block size and key sizes of 128, 192, and 256 bits. As the hardware version of cipher implementation is getting popular, the Camellia hardware design should be constantly improved in terms of performance. The key aim of this research is to design and implement the improved version of Camellia cipher using custom-based approach based on 0.18μm technology. The new hardware Camellia design is synthesized using timing, area and power constraints to achieve less area, less power and high-speed design. Finally the results are been compared and analyzed with previous implementation in terms of performance parameters. The design is described using Verilog HDL and been verified using functional simulation from the Modelsim-Intel FPGA, while Synopsys had been utilized for synthesis process. Based on the generated synthesis reports, the total area consumed by the design on ASIC platform is 1294.11-unit area with a total cell area of 1176.25-unit area, while the total power consumption is 0.1245mW, and an increased speed of more than 80% as compared to previous design. In conclusion, this design had achieved better performance compared to previous design.
      2  6
  • Publication
    IoT Monitoring System for Fig in Greenhouse Plantation
    ( 2023-07-01)
    Mohd Firdaus Ibrahim
    ;
    Muammar Mohamad Isa
    ;
    Razaidi Hussin
    ;
    Syed Muhammad Mamduh Syed Zakaria
    ;
    Norhawati Ahmad
    ;
    Yuan C.K.J.
    ;
    Abdullah A.F.T.
    Fig is rich in nutrients and has a high market value due to its extensive application in promoting a nutritious food supply and supporting various medical disciplines. However, the equatorial climate in Malaysia poses significant difficulties for the large-scale cultivation of figs. Therefore, a Smart Monitoring System for controlled Greenhouse Plantation was proposed in this study to enable more efficient cultivation. The proposed system was equipped with LoRa and GSM to overcome the distance and data transmission limitations, developed using the Arduino Uno microcontroller. The proposed system consists of sensors to measure soil moisture, temperature, and humidity, while the data is transmitted using long-range LoRa communication to the control unit. The sensors circuit also has a solar power supply for convenient application in rural areas. The control unit is placed at a location with good data coverage. The system functioned well, and the monitoring parameter was accurately read, collected, and updated every 30 minutes. The optimal temperature, humidity, and soil moisture for growing fig is 22°C-33°C, > 60%, and 50%-60%, respectively. Real-time data monitoring enabled the sensors and control unit to achieve LoRa data transmission over a distance of 2.5 km. Any data exceeding the controlled parameters will trigger an alarm so that the user can perform corrective actions.
      2  33
  • Publication
    Development of fruits artificial intelligence segregation
    ( 2021-12)
    Norhidayah Mohd Rozi
    ;
    Razaidi Hussin
    ;
    Muammar Mohamad Isa
    ;
    Syed Muhammad Mamduh Syed Zakaria
    ;
    Afzan Kamarudin
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Siti Zarina Md Naziri
    Higher output was needed as technology advance to meet human needs and industry demands. Fruits Artificial Intelligence Segregation (FAIS) is a project that uses image processing to detect and differentiate between various types of fruits. This paper proposes an OpenCV python, and the Convolution Neural Network (CNN) is used to complete the segregation of multiple fruits. The code extracts the fruit's characteristics and separates them based on their color and shape once placed in front of the camera to implement liveness detection. This paper shows the accuracy and reliability of the Fruits Artificial Intelligence Segregation (FAIS) system based on the number of datasets.
      1  25