Camellia cipher is another symmetric block cipher which allows the encryption and decryption process to share the same key. The cipher permits a 128-bits input data with three different key size: 128, 192 and 256 bits. This paper presents two hardware design approach of Camellia cipher, which are FPGA and custom-based design approach. These approaches utilized design softwares of Altera Quartus II with device family of Cyclone II and Synopsys Design Compiler. The performance of Camellia crypto-core design is then been evaluated based on the implementation platform in terms of speed, area and power. With an equal base of 50MHz of clock frequency, custom-based design is found more efficient than FPGA-based design due to the execution time achieved with 8.46ns, which is faster than the latter that consumed double the time with 16.075ns. The custom-based design achieved 15.13 Gbps of throughput. Besides, the power consumption of custom-based design is 1.3519 mW which is lower than the FPGA-based design. In a nutshell, the design has successfully done as it achieved expected encryption and decryption outcomes with acceptable performance.
