Azizi Harun
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Preferred name
Azizi Harun
Official Name
Azizi, Harun
Alternative Name
Harun, Azizi
Harun, A.
Bin Harun, Azizi
Main Affiliation
Scopus Author ID
15063856600
Researcher ID
V-6892-2019

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Now showing 1 - 10 of 11
  • Publication
    Electrical conductivity (EC) sensing system for paddy plant using the internet of things (IoT) connectivity
    ( 2020-01-08)
    Othaman N.N.C.
    ;
    Mohd Nazrin Md Isa
    ;
    Sohiful Anuar Zainol Murad
    ;
    Azizi Harun
    ;
    Shaiful Nizam Mohyar
    This paper presents the design and development of an IoT-based electrical conductivity system for measuring paddy soil nutrients. Relationship between electrical conductivity (EC) and the influence of soil temperature in precision farming will be discussed. In this work, the EC algorithm was modelled and verified using MATLAB and realized on Node MCU (ESP8266) microcontroller. Results showed that the measured data from the developed system is closed to the calibration solution conductivity that is 1.413mS/cm and 12.88mS/cm. It is also noted that the recorded electrical conductivity value increases with temperature.
  • Publication
    Signal propagation modelling for vehicle-to-infrastructure communication under the influence of metal obstruction
    ( 2021-12)
    Jamie Siregar Cynthia Turner
    ;
    Shahriman Abu Bakar
    ;
    Azizi Harun
    ;
    Mohd Sani Mohamad Hashim
    ;
    Zuradzman Mohamad Razlan
    ;
    D L Ndzi
    ;
    Rizalafande Che Ismail
    ;
    Sohiful Anuar Zainol Murad
    ;
    Mohd Nazrin Md Isa
    ;
    Shaiful Nizam Mohyar
    ;
    Mohammad Fadzli Ramli
    ;
    M K N Zulkifli
    Connected car has become one of emerging technology in the automotive industries today. This development preludes a rise in vehicular communication studies that primarily targets radio channel modelling on vehicle-to-vehicle (V2V) and vehicle-to-infrastructure (V2I) communication mode. Considering vehicular obstruction, vast channel propagation studies have focused more on V2V mode while others consider the typical urban scenarios consisting of high traffic volumes of moving vehicles. Due to challenging propagation mechanisms and high complexity in such areas, radio propagation models applied in simulators assume an obstacle-free environment rather than considering the least effect imposed by metal obstruction on communication signal. Besides, there are limited studies pertaining to metal obstruction that considers several under-explored environments such as actual parking lots, junctions and other road infrastructure support. As such, this paper demonstrates signal attenuation analysis caused by the presence of metal objects in low density over obstacle-free environment on actual parking lot via V2I mode. Two scenarios such as LOS and NLOS conditions consisting of obstacle-free, cars and buses as static metal objects are evaluated. The aim of this research is to characterize signal strength caused by metal blockage on radio wave propagation predicated on the presence of vehicles as a subject of obstruction in comparison to obstacle-free vehicular environment. The validity of data is shown through received signal strength indicator (RSSI) and approximation analysis (RMSE) to demonstrate the efficiency of obtained measurements. The results demonstrated that Log-normal shadowing model yields the best fit to low-density metal obstruction scenario with smallest RMSE of 4.78 under bus obstruction whereas 5.72 under car obstruction.
      5  22
  • Publication
    Speed and Area Efficient FXP Adders and Multipliers: A Comparative Analysis for LNS System
    ( 2020-12-18)
    Basir M.S.S.M.
    ;
    Rizalafande Che Ismail
    ;
    Siti Zarina Md Naziri
    ;
    Mohd Nazrin Md Isa
    ;
    Sohiful Anuar Zainol Murad
    ;
    Azizi Harun
    In this paper, a variety of adder and multiplier are compared to be implemented in a new logarithmic number system (LNS). Both adder and multiplier are designed with a generic very high-speed integrated circuit hardware description language (Verilog) program. This makes it possible to achieve the optimum performance in latency and area of 0.18µm CMOS technologies LNS chip. Consequently, the optimal configurations vary with speed and area of the schemes and in some cases can be compact area, O(n), fast in latency O(log2 n) or optimized. The program was scripted based on fixed-point (FXP) adders and multipliers that yet will be implemented in LNS system. The functionality of the scheme was tested before synthesized. Outcomes show that Ladner Fisher (LF) adder and modified Baugh Wooley multiplier contribute to fast in latency and consume minimal area.
      4  24
  • Publication
    Design of 5 V DC to 20 V DC switching regulator for power supply module
    ( 2017)
    Nor Afiqah Azmi
    ;
    Sohiful Anuar Zainol Murad
    ;
    Azizi Harun
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    M. A. Zulkifeli
    This paper presents the design of 5 V to 20 V DC switching regulator for power supply module. A voltage multiplier which consists of cascaded diode-capacitor combination is used in order to obtain a high voltage power supply. Due to power loss that has occurred in a stray of component arrangement, the proposed design employs a pulse width modulation (PWM) controller circuit with an inclusion of a capacitor, diode, and inductor components. The input supply of 5 V DC to LT1618 controller circuit has produced 20.35 V based from simulation results. Meanwhile, the measurement results of 19.36 V are obtained and the feedback signal is required for the purpose of stabilizing the output. The proposed design can reduce the components as well as the PCB size, thus minimizing the overall cost of making a switching regulator for power supply module. © 2017 Author(s).
      31  1
  • Publication
    Design and development of stingless beehive air pollutant monitoring system
    ( 2021-12)
    Mohammad Fadzli Ramli
    ;
    Azizi Harun
    ;
    Rizalafande Che Ismail
    ;
    Ndzi, David Lorater
    ;
    Turner, Jamie Siregar Cynthia
    ;
    Rohani S Mohamed Farook
    ;
    Mohd Nazrin Md Isa
    ;
    Sohiful Anuar Zainol Murad
    Currently, the presence and levels of air pollution in most stingless bee farms are not measured periodically nor there are proper monitoring levels that can be attributed to hive productivity. Long-term measurement and monitoring of air pollution for hive productivity and honey yield have not been performed. Therefore, this research proposes long-term and real-time air pollution measurement and monitoring techniques that are important for correlation analysis and parameter modeling. By using air pollution detection sensors through a wireless sensor network topology in stingless bee farms, details of pollutant presence and levels will be available in real-time over a long period of time for hive productivity correlation analysis. With such deployment using IoT -based systems, data can be easily accessed from anywhere thus ensuring data continuity. This paper describes a preliminary study on the design, development, and testing of real-time air pollution measurement and monitoring systems capable of determining the health status of stingless bee nests in mixed livestock crop farms. The goal of this research is to help beekeepers/users maintain control and be able to take quick action on the hive from the information obtained.
      2  51
  • Publication
    Development of Soil Electrical Conductivity (EC) Sensing System in Paddy Field
    ( 2021-03-01)
    Othaman N.N.C.
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    ;
    Rizalafande Che Ismail
    ;
    Siti Zarina Md Naziri
    ;
    Sohiful Anuar Zainol Murad
    ;
    Azizi Harun
    ;
    Muhammad Imran Ahmad
    The amount of fertilisers affects electrical conductivity (EC), and it is one of the major causes of the paddy yield decrease. The overuse of fertilisers can lead to environmental pollution and contamination. This study designed to develop soil electrical conductivity (EC) sensing system in the paddy field using the smart farming application. In this work, the study conducted in Kampung Ladang, Kuala Perlis, and the soil samples collected from a random location at two different depths from the paddy field. The EC value for the developed system was near the calibration solutions (12880µS and 150000µS) and directly proportional to the temperature. From the laboratory soil results, the EC values of the soils were higher with fertiliser. However, the EC values for 0-10cm soil depth were higher than 10-20cm soil depth. The soil EC is inversely proportional to the depth of soil and directly proportional to the amount of nutrients. It observed that the soil EC is linearly related to the amount of nutrients and temperature. The EC value decreases with the increase of soil depth displays a low amount of salts in the deep soil, while, increases with the increase of temperature indicates high current flow.
      1  38
  • Publication
    Design of CMOS low-dropout voltage regulator for power management integrated circuit in 0.18-μm technology
    ( 2020-01-08)
    Sohiful Anuar Zainol Murad
    ;
    Azizi Harun
    ;
    Mohd Nazrin Md Isa
    ;
    Shaiful Nizam Mohyar
    ;
    Sapawi R.
    ;
    Karim J.
    A low-dropout (LDO) voltage regulator is the main component used in the majority of portable electronic application since it is used as power management unit in those applications. In this paper, a LDO regulator for the power management integrated circuit in 0.18-μm CMOS technology using Cadence software is presented. The error amplifier of the proposed LDO employed seven transistors for current mirror. Meanwhile, the PMOS transistor is used as a pass element transistor to control the voltage variation. The resistors are used as a feedback network circuit while the capacitor is used to minimise the variation of output voltage. The simulation results show that the proposed design provides a 2.41 V constant output voltage for the supply voltage ranges of 2.55 V to 3.55 V. The dropout voltage of 140 mV is achieved with 1.48 mW power consumption. The line regulation is 1.0 mV/V and the load regulation is 0.41 mV/A, while the layout of the proposed regulator is 27 μm × 34 μm.
      1  26
  • Publication
    Design of 3.1-6.0 GHz CMOS ultra-wideband low noise amplifier with forward body bias technique for wireless applications
    ( 2020-01-08)
    Halim N.F.A.B.
    ;
    Sohiful Anuar Zainol Murad
    ;
    Azizi Harun
    ;
    Mohd Nazrin Md Isa
    ;
    Shaiful Nizam Mohyar
    ;
    Anishaziela Azizan
    This paper presents a design of 3.1-6.0 GHz CMOS ultra-wideband low noise amplifier (UWB LNA) with forward body bias technique for wireless applications. The UWB LNA is designed and simulated using 0.13-μm technology in Cadence software. The proposed UWB LNA consists of two stage common-source (CS) amplifiers with a forward body bias technique. A source degenerated inductor is used at the first stage to achieve a wideband input matching and high linearity. At the second stage, a shunt-peaking inductor is employed to enhance gain at higher frequency. The simulation results indicate that the proposed UWB LNA achieves a power gain (S21) of 10 dB, an input return loss (S11) is less than -5 dB, a minimum noise figure (NF) of 8.5 dB in the frequency range of 3.1- 6.0 GHz with power dissipation of 17.2 mW. The linearity analysis shows a 1 dB compression point (P1dB) of -9 dBm and the third-order intermodulation intercept points (IIP3) of 4 dBm are achieved. The proposed UWB LNA's layout is 0.68 mm2.
      2  27
  • Publication
    A very low-dropout voltage regulator in 0.18-μm CMOS technology for power management system
    ( 2020-07-01)
    Sohiful Anuar Zainol Murad
    ;
    Azizi Harun
    ;
    Mohd Nazrin Md Isa
    ;
    Shaiful Nizam Mohyar
    ;
    Karim J.
    A low dropout (LDO) voltage regulator is a type of voltage regulator circuit that works well even when the output voltage is very close to the input voltage, improving its power efficiency. This paper proposes the LDO voltage regulator in 0.18-μm CMOS technology. The proposed LDO regulator consists of voltage reference, symmetrical operational transconductance amplifier (OTA), PMOS transistor, resistive feedback network and output capacitor. The NMOS symmetrical OTA is implemented as an error amplifier and a PMOS transistor is employed as a pass device to improve gain and minimize low dropout voltage, respectively. The proposed design is simulated using Spectre simulator in Cadence software to verify its regulator performance. The simulation results show that the proposed LDO is capable to operate from a supply voltage of 1.7-2.0 V with a low dropout voltage of 19.3 mV at a maximum 50 mA load current to regulate output voltage 1.5 V. The active chip is 2.96 mm2 in size. The performance of the proposed LDO is suitable to enhance power management for system on chip (SoC) applications.
      1  17