Faizah Abu Bakar
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Preferred name
Faizah Abu Bakar
Official Name
Faizah, Abu Bakar
Alternative Name
Bakar, Faizah Abu
Bakar, F. A.
Main Affiliation
Scopus Author ID
36809027100
Researcher ID
DWO-5731-2022

Research Output

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  • Publication
    Design of low power Wallace tree multiplier using modified full adder
    ( 2024-02-08)
    Ahmad Fariz Hasan
    ;
    Sohiful Anuar Zainol Murad
    ;
    Faizah Abu Bakar
    ;
    Husin M.F.C.
    ;
    Sapawi R.
    High speed and energy-efficient of a device are essential in the electronics industry due to the high demand for multimedia usage and fast technology. Multipliers play a vital role, especially in the processor's integrated circuits, microprocessors, filters, and arithmetic units. Wallace tree multiplier works in parallel, making it an efficient multiplier in terms of area and speed. Internally, a multiplier consists of Adder, which is full Adder (FA) and half Adder (HA). Full adders give a significant contribution to making a multiplier that works very well. A processor or chip performs very efficiently and effectively when running at high speed, in a small area, and at low power. Modification of full Adder in Wallace tree multiplier helps to consume low power during multiplication. In this project, 4-bit and 8-bit Wallace tree multipliers are designed. The design is developed in Verilog HDL and simulated the functionalities using Quartus II software. Mentor Graphic software was used to produce the final layout of 8 x 8-bit Wallace tree multiplier. The modified Wallace tree multiplier shows 64.97mW power lower than the conventional multiplier, which was 65.88mW.
  • Publication
    A Contemporary Review of High Voltage Partial Discharge Detection and Recognition Techniques
    ( 2023-07-01)
    Bohari Z.H.
    ;
    Muzamir Isa
    ;
    Faizah Abu Bakar
    ;
    Ahmad Zaidi Abdullah
    ;
    Ayob Nazmy Nanyan
    ;
    Nasir M.N.M.
    ;
    Sulaima M.F.
    ;
    Ahmad E.Z.
    This review article provides a summary of the most advanced approaches and advancements in the detection and recognition of high voltage partial discharge (PD). It discusses numerous detecting technologies, such as electrical, acoustic, and optical approaches, as well as their merits and disadvantages. It also discusses current developments in signal processing and pattern recognition algorithms used for PD detection and classification. Lastly, the study covers the challenges and limitations in high voltage PD detection and identification studies, as well as potential future solutions.
      1
  • Publication
    Design of High-Quality Factor Active Indictor Using CMOS 0.18-μm Technology for 5G Applications
    ( 2022-01-01)
    Ali H.A.A.A.
    ;
    Sohiful Anuar Zainol Murad
    ;
    Ahmad Fariz Hasan
    ;
    Faizah Abu Bakar
    ;
    Sapawi R.
    This paper presents high quality factor of active inductor circuit for 5G application. The proposed circuit is based on the differential active inductor (DAI) topology. The DAI is designed using CMOS 0.18 μm technology. The quality factor (Q) can be tuned with the current source values, ranging from 0.5 mA to 3 mA, while the voltage can control the inductance values L. Meanwhile, the frequency range can be controlled with the feedback resistance. The simulation results indicate that the Q factor as large as 262.5k can be achieved with inductor values of 10 nH at frequency 3.2 GHz. In addition, the Q factor of 1650 is obtained at 3.5 GHz. The performance comparison with previously published works is also demonstrated and found that the proposed DAI is suitable for 5G application.
      3
  • Publication
    A 28 GHz high efficiency fully integrated 0.18 µm combined CMOS power amplifier using power divider technique for 5G millimeter-wave applications
    ( 2020-04-01)
    Hasan A.F.
    ;
    Sohiful Anuar Zainol Murad
    ;
    Faizah Abu Bakar
    ;
    Zulkifli T.Z.A.
    A 28 GHz power amplifier (PA) using CMOS 0.18 µm Silterra process technology for milimeter wave applications is reported. Maximizing the power added efficiency (PAE) and output power are achieved by optimize the circuit with power divider and cascade configuration. In addition, reverse body bias is also employed for realizing excellent PAE and power consumption. A three stage CMOS PA with power combiner is designed and simulated. The simulation results show that the proposed PA consumes 62.56 mW and power gain (S21) of 8.08 dB is achieved at 28 GHz. The PA achieves saturated power (Psat) of 12.62 dBm and maximum PAE of 23.74% with output 1-dB compression point (OP1dB) 10.85 dBm. These results demonstrate the proposed power amplifier architecture is suitable for 5G applications.
      1
  • Publication
    Design of High-Quality Factor Active Indictor Using CMOS 0.18-μm Technology for 5G Applications
    ( 2022-01-01)
    Ali H.A.A.A.
    ;
    Sohiful Anuar Zainol Murad
    ;
    Hasan A.F.
    ;
    Faizah Abu Bakar
    ;
    Sapawi R.
    This paper presents high quality factor of active inductor circuit for 5G application. The proposed circuit is based on the differential active inductor (DAI) topology. The DAI is designed using CMOS 0.18 μm technology. The quality factor (Q) can be tuned with the current source values, ranging from 0.5 mA to 3 mA, while the voltage can control the inductance values L. Meanwhile, the frequency range can be controlled with the feedback resistance. The simulation results indicate that the Q factor as large as 262.5k can be achieved with inductor values of 10 nH at frequency 3.2 GHz. In addition, the Q factor of 1650 is obtained at 3.5 GHz. The performance comparison with previously published works is also demonstrated and found that the proposed DAI is suitable for 5G application.
  • Publication
    Compact Parallel Coupled Line Microstrip BPF Design for 5G Applications
    ( 2023-01-01)
    Anak Temuli H.U.
    ;
    Khairul Najmy Abdul Rani
    ;
    Fairul Afzal Ahmad Fuad
    ;
    Khairil Syahmi Musa
    ;
    Norfatihah Bahari
    ;
    Faizah Abu Bakar
    ;
    Mohd Aminudin Jamlos
    ;
    Rahayu Y.
    A compact parallel coupled line microstrip bandpass filter (BPF) for sub-6 GHz fifth generation (5G) applications is designed operating between edge frequencies of 3.40 and 3.80 GHz. The design is designed and simulated by means of the Advanced Design System (ADS) software using the flame retardant-4 (FR-4) board as the substrate. The BPF design applies the insertion loss method (ILM) to generate a parallel coupled line filter structure that performs passband permission and unwanted noise attenuation below 3.40 GHz and above 3.80 GHz, respectively. Consistent and relevant performances in terms of matching impedance, return loss (S11), insertion loss (S21), voltage standing wave ratio (VSWR), far field radiation pattern, gain, directivity, and radiated efficiency promise the microstrip BPF design has a potential for sub-6 GHz 5G applications.
  • Publication
    High linearity multi-band CMOS low noise amplifier at 2.4/3.5 GHz for 4G/5G applications
    ( 2024-02-08)
    Sohiful Anuar Zainol Murad
    ;
    Azizan A.
    ;
    Faizah Abu Bakar
    ;
    Ahmad Fariz Hasan
    ;
    Marzuki A.
    ;
    Zulkifli T.Z.A.
    This paper presents a high linearity multi-band CMOS low noise amplifier (LNA) at 2.4/3.5 GHz for wireless application. The proposed multi-band CMOS LNA is targeted for concurrent 2.4 GHz and 3.5 GHz bands for 4G and 5G wireless technology, respectively. A cascoded topology with bandpass and bandstop filter at the input is utilized to achieve multiple-band frequency at 2.4 GHz and 3.5 GHz. The LNA is implemented and simulated using CMOS 0.13 μm process in Cadence Virtuoso Analog Design Environment software. The simulation results indicate that the gain (S21) of 15 dB/11 dB with the third order intercept point (IIP3) of 2.04 dBm/3.80 dBm at 2.4 GHz/3.5 GHz frequencies are achieved. Meanwhile, the noise figure of 3.0 dB/3.6 dB is obtained with the power consumption of 35.1 mW at 1.0 V supply voltage. The total chip area is 2.61 mm2
  • Publication
    A 28 GHz 0.18-μm CMOS cascade power amplifier with reverse body bias technique
    ( 2019-08-01)
    Ahmad Fariz Hasan
    ;
    Sohiful Anuar Zainol Murad
    ;
    Faizah Abu Bakar
    A 28 GHz power amplifier (PA) using CMOS 0.18 μm Silterra process technology is reported. The cascade configuration has been adopted to obtain high Power Added Efficiency (PAE). To achieve low power consumption, the input stage adopts reverse body bias technique. The simulation results show that the proposed PA consumes 32.03mW and power gain (S21) of 9.51 dB is achieved at 28 GHz. The PA achieves saturated power (Psat) of 11.10 dBm and maximum PAE of 16.55% with output 1-dB compression point (OP1dB) 8.44 dBm. These results demonstrate the proposed power amplifier architecture is suitable for 5G applications.
      1
  • Publication
    Design of High-Speed Low Power CMOS Operational Amplifier Utilizing 0.18-µm Technology for ADC Applications
    ( 2023-10-06)
    Sohiful Anuar Zainol Murad
    ;
    Faizah Abu Bakar
    ;
    Jasri I.A.A.
    ;
    Zulkifli T.Z.A.
    ;
    Marzuki A.
    This paper presents a design of high-speed low power CMOS operational amplifier utilizing 0.18-µm technology for ADC applications. A folded cascode with PMOS configuration is chosen as a topology for the op-amp design which provides high-speed structure and more stable configuration compare to the other topologies. High-swing cascode current mirror is combined as a biasing circuit to provide proper voltage and stable output current for the op-amp structure. The proposed design is simulated in Cadence Virtuoso EDA tools software. The simulation results show the DC gain of 61.85 dB and phase margin (PM) of 88.34° with 0.5 pF load capacitor is achieved. Moreover, the slew rate and settling time of 120.125 V/µs and 20.3 ns are obtained, respectively. A low power consumption of 0.17 mW at supply voltage of 1.8 V indicates the low power is achieved in the circuit design. The proposed high speed low power CMOS op-amp is suitable for high-speed ADC applications.
      1
  • Publication
    A 3.5 GHz hybrid CMOS class E power amplifier with reverse body bias design for 5G applications
    ( 2021-05-03)
    Ahmad Fariz Hasan
    ;
    Sohiful Anuar Zainol Murad
    ;
    Faizah Abu Bakar
    A 3.5 GHz CMOS power amplifier (PA) using 0.18 μm Silterra process technology for 5G applications is reported. The proposed circuit consists of two stages. In the first stage, a cascade topology is adopted with a reverse body bias technique to obtain high voltage gain and minimize the current to reduce the power consumption. Meanwhile, a class-E is use in the second stage to obtain high efficiency. The simulation results of propose PA indicate that 22.6 dB of peak power gain (S21), 8.2 dBm of saturated power (Psat) and 54.6% of power added efficiency (PAE) is achieve at 3.5 GHz. These results prove that the proposed PA is suitable for low band 5G applications.
      1