A 3.5 GHz CMOS power amplifier (PA) using 0.18 μm Silterra process technology for 5G applications is reported. The proposed circuit consists of two stages. In the first stage, a cascade topology is adopted with a reverse body bias technique to obtain high voltage gain and minimize the current to reduce the power consumption. Meanwhile, a class-E is use in the second stage to obtain high efficiency. The simulation results of propose PA indicate that 22.6 dB of peak power gain (S21), 8.2 dBm of saturated power (Psat) and 54.6% of power added efficiency (PAE) is achieve at 3.5 GHz. These results prove that the proposed PA is suitable for low band 5G applications.
