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Rizalafande Che Ismail
Preferred name
Rizalafande Che Ismail
Official Name
Rizalafande, Che Ismail
Alternative Name
Ismail, Rizalafande C.
Rizalafande, Che Ismail
Chesmail, R.
Ismail, R. C.
Che Ismail, Rizalafande
Ismail, Rizalafande Che
Ismail, R. Che
Main Affiliation
Scopus Author ID
22634128600
Now showing
1 - 10 of 13
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Publication"Look & Blink" two step verification security log in system( 2021-03-01)
;Kai Qi L. ; ; ; ;Naziri S.Z.M.A new artificial intelligence security design which is face recognition with eye blinking login system is proposed. It aims to strengthen the security account for each user using artificial intelligence technology and increase speed and user convenience for security during login. The face of a person cannot be copied and it can replace the username of the user, while eye blinking detection is another step for double verification replacing the password of a user. It is a two-step verification process that can be applied to all sorts of account login field so that this technology can replace the old school username with a password security system. The recognition system used a real-time where it is reducing the number of hackers in the field as it is impossible to hack a person's real-time face. The proposed system has been tested and analyzed the functionality by accessing the personal account in the university's portal.2 38 -
PublicationDesign of multiplicative inverse value generator using logarithm method for AES algorithm( 2020)
;Goh Yie Yen ; ; ;Advanced Encryption Standard (AES) algorithm is one of the most widely used symmetric block cipher that is utilized in data protection through symmetric cryptography algorithm, as it offers high efficiency and ability in securing information. In AES, the SubByte/InvSubByte transformation costs an amount of memories for the lookup tables (LUT) that leads to area usage in hardware. As per mathematical equations, the SubByte/InvSubByte is able to share the same resource which is the multiplicative inverse value table. Instead of using LUTs, the multiplicative inverse values can be generated on-the-fly as needed. Therefore, this paper presents the custom hardware design and implementation of multiplicative inverse value generator using logarithm method specifically for AES algorithm. The logarithm method benefits the usage of antilog and log values in obtaining the multiplicative inverse value. The EDA tools as Intel Quartus Prime, Synopsys Design Compiler and IC Compiler are used to perform functional simulation, on synthesis analysis and block-level implementation. Detailed comparison is made between this work and previous implementation. The newly designed multiplicative inverse value generator has achieved the improvement on speed and area as compared to previous implementation. The area of the design is reduced around 8.5% with current improvement of 63.091 μm2, while the speed has increased to 2.54 ns with a positive slack of 0.11 ns, which is shorter than the previous implementation. The new design also outreached the performance of the common LUT-based design. © 2020 IEEE.34 3 -
PublicationFace Recognition and Identification using Deep Learning Approach( 2021)
;KH Teoh ; ; ; ;Muhammad Sufyan Safwan BasirHuman face is the significant characteristic to identify a person. Everyone has their own unique face even for twins. Thus, a face recognition and identification are required to distinguish each other. A face recognition system is the verification system to find a person’s identity through biometric method. Face recognition has become a popular method nowadays in many applications such as phone unlock system, criminal identification and even home security system. This system is more secure as it does not need any dependencies such as key and card but only facial image is needed. Generally, human recognition system involves 2 phases which are face detection and face identification. This paper describes the concept on how to design and develop a face recognition system through deep learning using OpenCV in python. Deep learning is an approach to perform the face recognition and seems to be an adequate method to carry out face recognition due to its high accuracy. Experimental results are provided to demonstrate the accuracy of the proposed face recognition system.2 21 -
PublicationArea optimization of active reference band gap amplifier in cadence virtuoso( 2024-02-08)
;Sheng T.W. ; ; ; ; ; ;Band Gap Amplifier is mostly used in integrated circuit (IC) chips. It is commonly used to generate temperature independent reference voltage. Band Gap Amplifier is essential and implemented widely in analog and digital circuits because it is temperature independent thus produces low voltage. In this work, layout of active reference band gap amplifier is designed in cadence virtuoso and the percentages of differences sizes of layouts are compared. The different versions of layout design are compared in the result to show the percentages of area optimization. The main layout designs such as layout 1 (without sharing source, drain and well), layout 2 (sharing source, drain without sharing wells), and layout 3 (share the source, drain, and well) are designed to get the comparison of area optimization. The results show that there is 27.73% reduction overall layout by applied several techniques to optimize the area in layout design in order to get a compactable layout.6 35 -
PublicationHardware Design of Combinational 128-bit Camellia Symmetric Cipher using 0.18μm Technology(Institute of Electrical and Electronics Engineers Inc., 2022-01-01)
;Sak C.U. ; ; ;Camellia is another symmetric key block cipher with a 128-bit block size and key sizes of 128, 192, and 256 bits. As the hardware version of cipher implementation is getting popular, the Camellia hardware design should be constantly improved in terms of performance. The key aim of this research is to design and implement the improved version of Camellia cipher using custom-based approach based on 0.18μm technology. The new hardware Camellia design is synthesized using timing, area and power constraints to achieve less area, less power and high-speed design. Finally the results are been compared and analyzed with previous implementation in terms of performance parameters. The design is described using Verilog HDL and been verified using functional simulation from the Modelsim-Intel FPGA, while Synopsys had been utilized for synthesis process. Based on the generated synthesis reports, the total area consumed by the design on ASIC platform is 1294.11-unit area with a total cell area of 1176.25-unit area, while the total power consumption is 0.1245mW, and an increased speed of more than 80% as compared to previous design. In conclusion, this design had achieved better performance compared to previous design.2 6 -
PublicationDevelopment of fruits artificial intelligence segregation( 2021-12)
;Norhidayah Mohd Rozi ; ; ; ; ; ;Higher output was needed as technology advance to meet human needs and industry demands. Fruits Artificial Intelligence Segregation (FAIS) is a project that uses image processing to detect and differentiate between various types of fruits. This paper proposes an OpenCV python, and the Convolution Neural Network (CNN) is used to complete the segregation of multiple fruits. The code extracts the fruit's characteristics and separates them based on their color and shape once placed in front of the camera to implement liveness detection. This paper shows the accuracy and reliability of the Fruits Artificial Intelligence Segregation (FAIS) system based on the number of datasets.1 25 -
PublicationHardware Design of Combinational 128-bit Camellia Symmetric Cipher using 0.18µm Technology( 2022)
;Chawalit Udom Sak ; ; ;Camellia is another symmetric key block cipher with a 128-bit block size and key sizes of 128, 192, and 256 bits. As the hardware version of cipher implementation is getting popular, the Camellia hardware design should be constantly improved in terms of performance. The key aim of this research is to design and implement the improved version of Camellia cipher using custom-based approach based on 0.18µm technology. The new hardware Camellia design is synthesized using timing, area and power constraints to achieve less area, less power and high-speed design. Finally the results are been compared and analyzed with previous implementation in terms of performance parameters. The design is described using Verilog HDL and been verified using functional simulation from the Modelsim-Intel FPGA, while Synopsys had been utilized for synthesis process. Based on the generated synthesis reports, the total area consumed by the design on ASIC platform is 1294.11-unit area with a total cell area of 1176.25-unit area, while the total power consumption is 0.1245mW, and an increased speed of more than 80% as compared to previous design. In conclusion, this design had achieved better performance compared to previous design.3 19 -
PublicationDevelopment of Soil Electrical Conductivity (EC) Sensing System in Paddy Field( 2021-03-01)
;Othaman N.N.C. ; ; ; ; ; ;The amount of fertilisers affects electrical conductivity (EC), and it is one of the major causes of the paddy yield decrease. The overuse of fertilisers can lead to environmental pollution and contamination. This study designed to develop soil electrical conductivity (EC) sensing system in the paddy field using the smart farming application. In this work, the study conducted in Kampung Ladang, Kuala Perlis, and the soil samples collected from a random location at two different depths from the paddy field. The EC value for the developed system was near the calibration solutions (12880µS and 150000µS) and directly proportional to the temperature. From the laboratory soil results, the EC values of the soils were higher with fertiliser. However, the EC values for 0-10cm soil depth were higher than 10-20cm soil depth. The soil EC is inversely proportional to the depth of soil and directly proportional to the amount of nutrients. It observed that the soil EC is linearly related to the amount of nutrients and temperature. The EC value decreases with the increase of soil depth displays a low amount of salts in the deep soil, while, increases with the increase of temperature indicates high current flow.1 38 -
PublicationA Real-Time distance prediction via deep learning and microsoft kinect( 2022)
;Hwee Sheng Tham ;3D(Dimension) understanding has become the herald of computer vision and graphics research in the era of technology. It benefits many applications such as autonomous cars, robotics, and medical image processing. The pros and cons of 3D detection bring convenience to the human community instead of 2D detection. The 3D detection consists of RGB (Red, Green and Blue) colour images and depth images which are able to perform better than 2D in real. The current technology is relying on the high costing light detection and ranging (LiDAR). However, the use of Microsoft Kinect has replaced the LiDAR systems for 3D detection gradually. In this project, a Kinect camera is used to extract the depth of image information. From the depth images, the distance can be defined easily. As in the colour scale, the red colour is the nearest and the blue colour is the farthest. The depth image will turn black when reaching the limitation of the Kinect camera measuring range. The depth information collected will be trained with deep learning architecture to perform a real-time distance prediction.2 25 -
PublicationLess memory and high accuracy logarithmic number system architecture for arithmetic operations( 2021-09-01)
; ; ;Interpolation is another important procedure for logarithmic number system (LNS) addition and subtraction. As a medium of approximation, the interpolation procedure has an urgent need to be enhanced to increase the accuracy of the operation results. Previously, most of the interpolation procedures utilized the first degree interpolators with special error correction procedure which aim to eliminate additional embedded multiplications. However, the interpolation procedure for this research was elevated up to a second degree interpolation. Proper design process, investigation, and analysis were done for these interpolation configurations in positive region by standardizing the same co-transformation procedure, which is the extended range, second order co-transformation. Newton divided differences turned out to be the best interpolator for second degree implementation of LNS addition and subtraction, with the best-achieved BTFP rate of +0.4514 and reduction of memory consumption compared to the same arithmetic used in european logarithmic microprocessor (ELM) up to 51%.34 2