Siti Zarina Md Naziri
Thumbnail Image
Preferred name
Siti Zarina Md Naziri
Official Name
Siti Zarina, Md Naziri
Alternative Name
Naziri, S. Z.M.
Naziri, S. Z. M.
Main Affiliation
Scopus Author ID
26428387900

Research Output

Filters

26 1 1
1
26
Reset filters

Settings
Now showing 1 - 10 of 26
  • Publication
    Arithmetic addition and subtraction function of logarithmic number system in positive region: An investigation
    ( 2015)
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Ali Yeon Md Shakaff
    Logarithmic number system or LNS has become an optimal choice in digital image processing instead of floating point (FP) system based on latest researches in LNS. Digital image processing which deals with a lot of complex operations such as multiplication and division, makes LNS as a great choice of implementation. However, the implementation had been restricted by the addition and subtraction function in LNS arithmetic as these functions entail complex procedures and circuitry. As its huge potential to be a substitution of FP, there is an urgent need for LNS to improve the performance of both operations. Hence, various studies had been conducted in this area, however most of the research concern the implementation of these operations in the negative region. Therefore, this study is conducted with the objective on the exploration of both LNS addition and subtraction operations in the positive region and highlights the potential areas for design modifications and improvements. Then, these enhancements will be combined with other arithmetic functions in creating an optimum LNS design to be utilized in any digital image processing system.
  • Publication
    Design and comparison of 8-bit hybrid and fixed point arithmetic unit
    ( 2020-01-08)
    Sugumaran P.
    ;
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    An arithmetic unit of the arithmetic logic unit (ALU) plays a significant role in performing arithmetic operations. Most of the recent arithmetic units are implemented based on floating point (FLP) or fixed point (FXP) systems. However, the multiplication and division operation of FLP and FXP systems have some restriction in offering the best performance on speed and area compared to their excellent performance of their addition and subtraction operations. Hence, the hybrid arithmetic unit is an option to offer as it combines the strength of the FXP system for the addition and subtraction operation and logarithmic number system (LNS) for the multiplication and division operation. LNS has the advantage in performing multiplication and division function by substituting these operations into FXP addition and subtraction respectively. Hence, this work presented an 8-bit hybrid arithmetic unit design that performs on four main arithmetic operations: addition, subtraction, multiplication and division. The multiplication and division operations are carried out under LNS by utilizing the Mitchell algorithm, while the addition and subtraction functions are conducted in FXP system. Both hybrid and FXP arithmetic unit are designed with suitable adders, multiplexers and combinational logics. Both arithmetic units are compared in terms of various hardware parameters such as area, cell, timing and power. Both designs are described in Verilog hardware description language (HDL) and functionally simulated and verified using the ModelSim software. The design were then been synthesized using the Synopsys Design Compiler in 0.13 μm TSMC technology. The synthesis results had proven that the designed hybrid arithmetic unit offers better performance compared to FXP arithmetic unit as it produced smaller area, higher speed, less timing and lower power consumption than the FXP arithmetic unit. As a conclusion, the hybrid arithmetic unit is more efficient and profitable than the solely used FXP arithmetic unit.
  • Publication
    Design and Analysis of 32-Bit Signed and Unsigned Multiplier Using Booth, Vedic and Wallace Architecture
    ( 2021-03-01)
    Yong K.M.
    ;
    Razaidi Hussin
    ;
    Afzan Kamarudin
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Siti Zarina Md Naziri
    This paper presents the implementation and performance comparison of the Booth encoding technique and Wallace Tree reduction scheme on Vedic architecture. The radix-4 Booth encoder is widely used to enhance the multiplication speed as it has the capability to reduce the number of partial products generated by half. Vedic multiplier partitions the inputs into two blocks to speed up the partial product generation and Wallace Tree reduction scheme speed up the partial product addition process by eliminating the carry chain of the addition. Radix-4 Booth encoding scheme Vedic multiplier with and without Wallace Tree partial product reduction scheme for signed and unsigned multiplication was designed and synthesized in Synopsys 130 nm technology. For unsigned multiplier, the Booth-Vedic multiplier is 37.29% faster and 26.13% smaller while the Booth-Vedic-Wallace multiplier is 39.79% faster and 28.81% smaller when compared with Vedic multiplier. The performance of both multipliers was dropped when used in signed multiplication due to signed extension during the partial product addition process. All the multiplier is functionally verified using modified testbench that is based on the concept of UVM testbench.
  • Publication
    Image data compression using fast Fourier transform (FFT) technique for wireless sensor network
    ( 2024-02-08)
    Haron M.H.
    ;
    Mohd Nazrin Md Isa
    ;
    Muhammad Imran Ahmad
    ;
    Arshad M.A.M.
    ;
    Asral Bahari Jambek
    ;
    Siti Zarina Md Naziri
    ;
    Hussin R.
    ;
    Harun A.
    ;
    Rizalafande Che Ismail
    ;
    Shaiful Nizam Mohyar
    Agricultural settings present unique challenges for the transmission of huge amounts of images over long-range wireless networks. It is challenging to remotely gather data for transmission over a wireless network in research areas due to a lack of basic amenities like internet connections, especially in distant agricultural areas. In this research, the Fast Fourier Transform (FFT) method was used in conjunction with the Discrete Cosine Transform (DCT) method of image compression to achieve a higher compression ratio. In order for a Wireless Sensor Network (WSN) to provide compressed image data to a wireless based station, a LoRaWAN network has been identified. Low-power LoRaWAN networks may regularly transmit compressed images from an agricultural region to a monitoring system up to 15 km away. Images of golden apple snails were collected for this study from a variety of sources. The procedure was coded in MATLAB so that it could be run with input images being judged by the created algorithm. The input images can be compressed with a range of compression ratios (CR) from 3.00 to 50.00, as shown by the simulation results. Compressed image quality is measured not only by the above-mentioned criteria, but also by Mean Square Error (MSE) and Peak Signal to Noise Ratio (PSNR). According to the numbers, the best achievable compression ratio is 49.04, with an MSE of 172.72 and a PSNR of 25.75 at its highest.
  • Publication
    An implementation of Short Time Fourier Transform for Harmonic Signal Detection
    ( 2021-03-01)
    Basir M.S.S.M.
    ;
    Rizalafande Che Ismail
    ;
    Yusof K.H.
    ;
    Katim N.I.A.
    ;
    Mohd Nazrin Md Isa
    ;
    Siti Zarina Md Naziri
    Power electronic components has the tendency to induce a non-linear signal called harmonic distortion. Without proper monitoring tools, harmonic distortion can harm sensitive electronic equipment, and in worse case scenarios, may lead to unreliable operation of controller and misalignment of motoring unit. This matter can be compromised by taking safety precaution, by identifying the level of harmonic rise in the electrical system. This paper presents analysis on different characteristics of harmonic signal using frequency distribution technique, namely Fourier transform (FT), and proposal of time-frequency distribution (TFD) technique, which is a short time Fourier transform (STFT). The novelty of utilizing STFT is the analyzed signal is represented in both time and frequency marginals, hence providing extra information of the spectral over the time. Simulation was carried out using MATLAB, by means the results consisting of the magnitude of multi-frequency components signal were represented in time-frequency representation (TFR). From the TFR, parameters such as instantaneous RMS fundamental voltage, V1RMS(t), instantaneous RMS voltage, VRMS(t), instantaneous total waveform distortion, VTWD(t), instantaneous total harmonic distortion, VTHD(t) and instantaneous total nonharmonic distortion, VTnHD(t) had been extracted. The performance of different harmonic signals such as normal, single-level harmonic, multi-level harmonic, short duration harmonic and interharmonic had been analyzed. The performance based on absolute percentage error (APE) index indicated average of 93% of correctness using 256 window length in STFT measurement.
  • Publication
    Less memory and high accuracy logarithmic number system architecture for arithmetic operations
    ( 2021-09-01)
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    Interpolation is another important procedure for logarithmic number system (LNS) addition and subtraction. As a medium of approximation, the interpolation procedure has an urgent need to be enhanced to increase the accuracy of the operation results. Previously, most of the interpolation procedures utilized the first degree interpolators with special error correction procedure which aim to eliminate additional embedded multiplications. However, the interpolation procedure for this research was elevated up to a second degree interpolation. Proper design process, investigation, and analysis were done for these interpolation configurations in positive region by standardizing the same co-transformation procedure, which is the extended range, second order co-transformation. Newton divided differences turned out to be the best interpolator for second degree implementation of LNS addition and subtraction, with the best-achieved BTFP rate of +0.4514 and reduction of memory consumption compared to the same arithmetic used in european logarithmic microprocessor (ELM) up to 51%.
  • Publication
    An Analysis of Interpolation Implementation for LNS Addition and Subtraction Function in Positive Region
    ( 2016)
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Ali Yeon Md Shakaff
    Interpolation is among of the most popular approach used in approximating the values in logarithmic number system (LNS) arithmetic design. This method that often combines with lookup tables (LUTs) manages to produce efficient LNS design in area, latency and accuracy. Current research proves that the combination of interpolators with co-transformation in LNS subtraction had shown extreme improvements in terms of speed and area, which is comparable to floating point (FLP) performance. Taking the advantage, this research had been conducted to analyze the implementation of these three interpolators, which are Taylor, Lagrange and modified Lagrange, in a 32-bit environment of the LNS addition and subtraction procedures with the first-order co-transformation in positive region. The designs were analyzed in two categories, which are the accuracy towards FLP and the total memory consumption. The best interpolator was selected based on the most optimum area consumption design with manageable accuracy in FLP limit. The outcome of this analysis could benefit further improvements in LNS design.
  • Publication
    Development of Soil Electrical Conductivity (EC) Sensing System in Paddy Field
    ( 2021-03-01)
    Othaman N.N.C.
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    ;
    Rizalafande Che Ismail
    ;
    Siti Zarina Md Naziri
    ;
    Sohiful Anuar Zainol Murad
    ;
    Azizi Harun
    ;
    Muhammad Imran Ahmad
    The amount of fertilisers affects electrical conductivity (EC), and it is one of the major causes of the paddy yield decrease. The overuse of fertilisers can lead to environmental pollution and contamination. This study designed to develop soil electrical conductivity (EC) sensing system in the paddy field using the smart farming application. In this work, the study conducted in Kampung Ladang, Kuala Perlis, and the soil samples collected from a random location at two different depths from the paddy field. The EC value for the developed system was near the calibration solutions (12880µS and 150000µS) and directly proportional to the temperature. From the laboratory soil results, the EC values of the soils were higher with fertiliser. However, the EC values for 0-10cm soil depth were higher than 10-20cm soil depth. The soil EC is inversely proportional to the depth of soil and directly proportional to the amount of nutrients. It observed that the soil EC is linearly related to the amount of nutrients and temperature. The EC value decreases with the increase of soil depth displays a low amount of salts in the deep soil, while, increases with the increase of temperature indicates high current flow.
  • Publication
    Face Recognition and Identification using Deep Learning Approach
    ( 2021)
    KH Teoh
    ;
    Rizalafande Che Ismail
    ;
    Siti Zarina Md Naziri
    ;
    Razaidi Hussin
    ;
    Mohd Nazrin Md Isa
    ;
    Muhammad Sufyan Safwan Basir
    Human face is the significant characteristic to identify a person. Everyone has their own unique face even for twins. Thus, a face recognition and identification are required to distinguish each other. A face recognition system is the verification system to find a person’s identity through biometric method. Face recognition has become a popular method nowadays in many applications such as phone unlock system, criminal identification and even home security system. This system is more secure as it does not need any dependencies such as key and card but only facial image is needed. Generally, human recognition system involves 2 phases which are face detection and face identification. This paper describes the concept on how to design and develop a face recognition system through deep learning using OpenCV in python. Deep learning is an approach to perform the face recognition and seems to be an adequate method to carry out face recognition due to its high accuracy. Experimental results are provided to demonstrate the accuracy of the proposed face recognition system.