The logarithmic number system (LNS) has gradually become an optimal choice in many design systems instead of the floating point (FLP) system based on latest researches in LNS. Intricate design areas such as digital image processing which deals with a lot of complex operations such as multiplication and division makes the LNS as a great choice of implementation. However, the implementation had been restricted by the addition and subtraction functions in the LNS arithmetic as these functions involve complex procedures and circuitry, together with massive storage. As the LNS has a huge potential to substitute the FLP, there is an urgent need to improve the LNS performance in both operations. Hence, various studies had been conducted in this area. However, most of the research are only concern with the implementation of these operations in the negative region. Therefore, this research is conducted with the objective on the exploration of both LNS addition and subtraction operations in the positive region. It also highlights the potential areas for design modifications and improvements of the key areas in both operations, which are the co-transformation and the interpolation functions. These enhancements are then implemented to these operations and the combination with other arithmetic functions represent an optimum LNS arithmetic unit which can be applied to any system design. Analysis shows that the LNS subtraction operation with expanded co-transformation range could achieve the precision within the FLP limit by taking the advantage of the range extension that is only possible to be realized in the positive region. In addition, the interpolation of up to second degree which is employed to both LNS addition and subtraction operations produces higher accuracy of +0.4514 as compared to previous research. In terms of hardware representation, the newly designed LNS arithmetic unit has shown a reduction of storage requirements by 5.6% and area consumption by 4.7% as compared to previous research. Meanwhile, the new LNS design requires 17.52 ns to compute a result by the contribution of the co-transformation function for the subtraction operation. The resulted worst-case delay has consumed 2.73 ns longer than previous research. Hence, the designed LNS architecture demonstrates its competency to be a replacement for the FLP-based systems with better performance in memory usage, silicon area and accuracy.
