Mohd Nazri Mohd Warip
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Preferred name
Mohd Nazri Mohd Warip
Official Name
Mohd Nazri , Mohd Warip
Alternative Name
Mohd Warip, Mohd Nazri
Mohd Warip, M. N.
Warip, M. N.
Warip, Mohd Nazri Mohd
Warip, Mohd Nazri bin Mohd
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Scopus Author ID
36555091900
Researcher ID
EDT-8958-2022

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  • Publication
    Multipoint Relay Path for Efficient Topology Maintenance Algorithm in Optimized Link State Routing-Based for VANET
    ( 2024-01-01)
    Waleed Khalid Ahmed
    ;
    Mohd Nazri Mohd Warip
    ;
    Mohamed Elshaikh Elobaid Said Ahmed
    ;
    Phak Len Al Eh Kan
    The Optimal Link State Routing (OLSR) protocol employs multipoint relay (MPR) nodes to disseminate topology control (TC) messages, enabling network topology discovery and maintenance. However, this approach increases control overhead and leads to wasted network bandwidth in stable topology scenarios due to fixed flooding periods. To address these challenges, this paper presents an Efficient Topology Maintenance Algorithm (ETM-OLSR) for Enhanced Link-State Routing Protocols. By reducing the number of MPR nodes, TC message generation and forwarding frequency are minimized. Furthermore, the algorithm selects a smaller subset of TC messages based on the changes in the MPR selection set from the previous cycle, adapting to stable and fluctuating network conditions. Additionally, the sending cycle of TC messages is dynamically adjusted in response to network topology changes. Simulation results demonstrate that the ETM-OLSR algorithm effectively reduces network control overhead, minimizes end-to-end delay, and improves network throughput compared to traditional OLSR and HTR-OLSR algorithms.
  • Publication
    Deep Learning with FPGA: Age and Gender Recognition for Smart Advertisement Board
    ( 2023-10-06)
    Yeoh W.S.
    ;
    Fazrul Faiz Zakaria
    ;
    Mustapa M.
    ;
    Mohd Nazri Mohd Warip
    ;
    Phak Len Al Eh Kan
    ;
    Mozi A.M.
    Age and gender recognition are helpful in various applications, especially in the field of advertising. To replace the traditional advertising method that can only display the same contents to all audiences, a smart advertisement board capable of detecting age and gender of audiences to display relevant contents is required to increase the effectiveness of advertising. This paper will use two image datasets to train and test the Convolutional Neural Network (CNN) based architecture models for age and gender recognition using deep learning. The dataset that produced the best performing model will be implemented on three different devices to observe the performance of the models on each device. A gender recognition model with accuracy of 91.53% and age recognition model with accuracy of 59.62% is produced. The results have also shown the use of Field Programmable Gated Array (FPGA) has greatly boosted the performance of the models in terms of throughput and latency.
      1
  • Publication
    Topology Design of Extended Torus and Ring for Low Latency Network-on-Chip Architecture
    ( 2017-06-01)
    Ng Yen Phing
    ;
    Mohd Nazri Mohd Warip
    ;
    Phak Len Al Eh Kan
    ;
    Farah W. Zulkefli
    ;
    R Badlishah Ahmad
    In essence, Network-on-Chip (NoC) also known as on-chip interconnection network has been proposed as a design solution to System-on-Chip (SoC). The routing algorithm, topology and switching technique are significant because of the most influential effect on the overall performance of Network-on-Chip (NoC). Designing of large scale topology alongside the support of deadlock free, low latency, high throughput and low power consumption is notably challenging in particular with expanding network size. This paper proposed an 8x8 XX-Torus and 64 nodes XX-Ring topology schemes for Network-on-Chip to minimize the latency by decrease the node diameter from the source node to destination node. Correspondingly, we compare in differences on the performance of mesh, full-mesh, torus and ring topologies with XX-Torus and XX-Ring topologies in term of latency. Results show that XX-Ring outperforms the conventional topologies in term of latency. XX-Ring decreases the average latency by 106.28%, 14.80%, 6.7 1%, 1.73%, 442.24% over the mesh, fully-mesh, torus, XX-torus, and Ring topologies.
  • Publication
    Imporved MPR selection algorithm-based WS-OLSR routing protocol
    ( 2024-05-01)
    Ahmed W.K.
    ;
    Mohd Nazri Mohd Warip
    ;
    Mohamed Elshaikh Elobaid Said Ahmed
    ;
    Phak Len Al Eh Kan
    Vehicle Ad Hoc Networks (VANETs) have become a viable technology to improve traffic flow and safety on the roads. Due to its effectiveness and scalability, the Wingsuit Search-based Optimised Link State Routing Protocol (WS-OLSR) is frequently used for data distribution in VANETs. However, the selection of MultiPoint Relays (MPRs) plays a pivotal role in WS-OLSR’s performance. This paper presents an improved MPR selection algorithm tailored to WS-OLSR, designed to enhance the overall routing efficiency and reduce overhead. The analysis found that the current OLSR protocol has problems such as redundancy of HELLO and TC message packets or failure to update routing information in time, so a WS-OLSR routing protocol based on improved-MPR selection algorithm was proposed. Firstly, factors such as node mobility and link changes are comprehensively considered to reflect network topology changes, and the broadcast cycle of node HELLO messages is controlled through topology changes. Secondly, a new MPR selection algorithm is proposed, considering link stability issues and nodes. Finally, evaluate its effectiveness in terms of packet delivery ratio, end-to-end delay, and control message overhead. Simulation results demonstrate the superior performance of our improved MR selection algorithm when compared to traditional approaches.
      1
  • Publication
    Toward Adaptive and Scalable Topology in Distributed SDN Controller
    ( 2023-03-01)
    Kelian V.H.
    ;
    Mohd Nazri Mohd Warip
    ;
    R Badlishah Ahmad
    ;
    Phak Len Al Eh Kan
    ;
    Fazrul Faiz Zakaria
    ;
    Mohd Zaizu Ilyas
    The increasing need for automated networking platforms like the Internet of Things, as well as network services like cloud computing, big data applications, wireless networks, mobile Internet, and virtualization, has driven existing networks to their limitations. Software-defined network (SDN) is a new modern programmable network architectural technology that allows network administrators to control the entire network consistently and logically centralized in software-based controllers and network devices become just simple packet forwarding devices. The controller that is the network's brain, is mostly based on the OpenFlow protocol and has distinct characteristics that vary depending on the programming language. Its function is to control network traffic and increase network resource efficiency. Therefore, selecting the right controllers and monitoring their performance to increase resource usage and enhance network performance metrics is required. For network performance metrics analysis, the study proposes an implementation of SDN architecture utilizing an open-source OpenDaylight (ODL) distributed SDN controller. The proposed work evaluates the deployment of distributed SDN controller performance on three distinct customized network topologies based on SDN architecture for node-to-node performance metrics such as delay, throughput, packet loss, and bandwidth use. The experiments are conducted using the Mininet emulation tool. Wireshark is used to collect and analyse packets in real-time. The results obtained from the comparison of networks are presented to provide useful guidelines for SDN research and deployment initiatives.
      1
  • Publication
    Breast cancer classification using deep learning and FPGA inferencing
    ( 2023-02-21)
    Wong E.H.
    ;
    Fazrul Faiz Zakaria
    ;
    Mustapa M.
    ;
    Mohd Nazri Mohd Warip
    ;
    Phak Len Al Eh Kan
    Implementing deep learning technology with FPGA as an accelerator has become a popular application due to its efficiency and performance. However, given the tremendous data generated on medical diagnosis, normal inference speed is not sufficient. Hence, the FPGA technology is implemented for fast inference. In this context, the FPGA accelerates the deep learning inference process for fast breast cancer classification with minimal latency on real-time deployment. This paper summarizes the findings of model deployment across various computing devices in deep learning technology with FPGA. The study includes model performance evaluation, throughput, and latency comparison with different batch sizes to the extent of expected delay for real-world deployment. The result concludes that FPGA is the most suitable to act as a deep learning inference accelerator with a high throughput-to-latency ratio and fast parallel inference.
      1