Mohd Nazrin Md Isa
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Mohd Nazrin Md Isa
Official Name
Mohd Nazrin , Md Isa
Alternative Name
Md Isa, Mohd N.
Isa, M. Nazrin Md
Md Isa, M. N.
Isa, Nazrin
Isa, M. Nazrin M.
Main Affiliation
Scopus Author ID
56426995200
Researcher ID
N-1250-2017

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  • Publication
    Design and Analysis of 32-Bit Signed and Unsigned Multiplier Using Booth, Vedic and Wallace Architecture
    ( 2021-03-01)
    Yong K.M.
    ;
    Razaidi Hussin
    ;
    Afzan Kamarudin
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Siti Zarina Md Naziri
    This paper presents the implementation and performance comparison of the Booth encoding technique and Wallace Tree reduction scheme on Vedic architecture. The radix-4 Booth encoder is widely used to enhance the multiplication speed as it has the capability to reduce the number of partial products generated by half. Vedic multiplier partitions the inputs into two blocks to speed up the partial product generation and Wallace Tree reduction scheme speed up the partial product addition process by eliminating the carry chain of the addition. Radix-4 Booth encoding scheme Vedic multiplier with and without Wallace Tree partial product reduction scheme for signed and unsigned multiplication was designed and synthesized in Synopsys 130 nm technology. For unsigned multiplier, the Booth-Vedic multiplier is 37.29% faster and 26.13% smaller while the Booth-Vedic-Wallace multiplier is 39.79% faster and 28.81% smaller when compared with Vedic multiplier. The performance of both multipliers was dropped when used in signed multiplication due to signed extension during the partial product addition process. All the multiplier is functionally verified using modified testbench that is based on the concept of UVM testbench.
  • Publication
    Image data compression using fast Fourier transform (FFT) technique for wireless sensor network
    ( 2024-02-08)
    Haron M.H.
    ;
    Mohd Nazrin Md Isa
    ;
    Muhammad Imran Ahmad
    ;
    Arshad M.A.M.
    ;
    Asral Bahari Jambek
    ;
    Siti Zarina Md Naziri
    ;
    Hussin R.
    ;
    Harun A.
    ;
    Rizalafande Che Ismail
    ;
    Shaiful Nizam Mohyar
    Agricultural settings present unique challenges for the transmission of huge amounts of images over long-range wireless networks. It is challenging to remotely gather data for transmission over a wireless network in research areas due to a lack of basic amenities like internet connections, especially in distant agricultural areas. In this research, the Fast Fourier Transform (FFT) method was used in conjunction with the Discrete Cosine Transform (DCT) method of image compression to achieve a higher compression ratio. In order for a Wireless Sensor Network (WSN) to provide compressed image data to a wireless based station, a LoRaWAN network has been identified. Low-power LoRaWAN networks may regularly transmit compressed images from an agricultural region to a monitoring system up to 15 km away. Images of golden apple snails were collected for this study from a variety of sources. The procedure was coded in MATLAB so that it could be run with input images being judged by the created algorithm. The input images can be compressed with a range of compression ratios (CR) from 3.00 to 50.00, as shown by the simulation results. Compressed image quality is measured not only by the above-mentioned criteria, but also by Mean Square Error (MSE) and Peak Signal to Noise Ratio (PSNR). According to the numbers, the best achievable compression ratio is 49.04, with an MSE of 172.72 and a PSNR of 25.75 at its highest.
  • Publication
    An implementation of Short Time Fourier Transform for Harmonic Signal Detection
    ( 2021-03-01)
    Basir M.S.S.M.
    ;
    Rizalafande Che Ismail
    ;
    Yusof K.H.
    ;
    Katim N.I.A.
    ;
    Mohd Nazrin Md Isa
    ;
    Siti Zarina Md Naziri
    Power electronic components has the tendency to induce a non-linear signal called harmonic distortion. Without proper monitoring tools, harmonic distortion can harm sensitive electronic equipment, and in worse case scenarios, may lead to unreliable operation of controller and misalignment of motoring unit. This matter can be compromised by taking safety precaution, by identifying the level of harmonic rise in the electrical system. This paper presents analysis on different characteristics of harmonic signal using frequency distribution technique, namely Fourier transform (FT), and proposal of time-frequency distribution (TFD) technique, which is a short time Fourier transform (STFT). The novelty of utilizing STFT is the analyzed signal is represented in both time and frequency marginals, hence providing extra information of the spectral over the time. Simulation was carried out using MATLAB, by means the results consisting of the magnitude of multi-frequency components signal were represented in time-frequency representation (TFR). From the TFR, parameters such as instantaneous RMS fundamental voltage, V1RMS(t), instantaneous RMS voltage, VRMS(t), instantaneous total waveform distortion, VTWD(t), instantaneous total harmonic distortion, VTHD(t) and instantaneous total nonharmonic distortion, VTnHD(t) had been extracted. The performance of different harmonic signals such as normal, single-level harmonic, multi-level harmonic, short duration harmonic and interharmonic had been analyzed. The performance based on absolute percentage error (APE) index indicated average of 93% of correctness using 256 window length in STFT measurement.
  • Publication
    Less memory and high accuracy logarithmic number system architecture for arithmetic operations
    ( 2021-09-01)
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    Interpolation is another important procedure for logarithmic number system (LNS) addition and subtraction. As a medium of approximation, the interpolation procedure has an urgent need to be enhanced to increase the accuracy of the operation results. Previously, most of the interpolation procedures utilized the first degree interpolators with special error correction procedure which aim to eliminate additional embedded multiplications. However, the interpolation procedure for this research was elevated up to a second degree interpolation. Proper design process, investigation, and analysis were done for these interpolation configurations in positive region by standardizing the same co-transformation procedure, which is the extended range, second order co-transformation. Newton divided differences turned out to be the best interpolator for second degree implementation of LNS addition and subtraction, with the best-achieved BTFP rate of +0.4514 and reduction of memory consumption compared to the same arithmetic used in european logarithmic microprocessor (ELM) up to 51%.
  • Publication
    Development of Soil Electrical Conductivity (EC) Sensing System in Paddy Field
    ( 2021-03-01)
    Othaman N.N.C.
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    ;
    Rizalafande Che Ismail
    ;
    Siti Zarina Md Naziri
    ;
    Sohiful Anuar Zainol Murad
    ;
    Azizi Harun
    ;
    Muhammad Imran Ahmad
    The amount of fertilisers affects electrical conductivity (EC), and it is one of the major causes of the paddy yield decrease. The overuse of fertilisers can lead to environmental pollution and contamination. This study designed to develop soil electrical conductivity (EC) sensing system in the paddy field using the smart farming application. In this work, the study conducted in Kampung Ladang, Kuala Perlis, and the soil samples collected from a random location at two different depths from the paddy field. The EC value for the developed system was near the calibration solutions (12880µS and 150000µS) and directly proportional to the temperature. From the laboratory soil results, the EC values of the soils were higher with fertiliser. However, the EC values for 0-10cm soil depth were higher than 10-20cm soil depth. The soil EC is inversely proportional to the depth of soil and directly proportional to the amount of nutrients. It observed that the soil EC is linearly related to the amount of nutrients and temperature. The EC value decreases with the increase of soil depth displays a low amount of salts in the deep soil, while, increases with the increase of temperature indicates high current flow.
  • Publication
    Face Recognition and Identification using Deep Learning Approach
    ( 2021)
    KH Teoh
    ;
    Rizalafande Che Ismail
    ;
    Siti Zarina Md Naziri
    ;
    Razaidi Hussin
    ;
    Mohd Nazrin Md Isa
    ;
    Muhammad Sufyan Safwan Basir
    Human face is the significant characteristic to identify a person. Everyone has their own unique face even for twins. Thus, a face recognition and identification are required to distinguish each other. A face recognition system is the verification system to find a person’s identity through biometric method. Face recognition has become a popular method nowadays in many applications such as phone unlock system, criminal identification and even home security system. This system is more secure as it does not need any dependencies such as key and card but only facial image is needed. Generally, human recognition system involves 2 phases which are face detection and face identification. This paper describes the concept on how to design and develop a face recognition system through deep learning using OpenCV in python. Deep learning is an approach to perform the face recognition and seems to be an adequate method to carry out face recognition due to its high accuracy. Experimental results are provided to demonstrate the accuracy of the proposed face recognition system.
  • Publication
    Design of Multiplicative Inverse Value Generator using Logarithm Method for AES Algorithm
    ( 2020-12-14)
    Yen, Goh Yie
    ;
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    Advanced Encryption Standard (AES) algorithm is one of the most widely used symmetric block cipher that is utilized in data protection through symmetric cryptography algorithm, as it offers high efficiency and ability in securing information. In AES, the SubByte/InvSubByte transformation costs an amount of memories for the lookup tables (LUT) that leads to area usage in hardware. As per mathematical equations, the SubByte/InvSubByte is able to share the same resource which is the multiplicative inverse value table. Instead of using LUTs, the multiplicative inverse values can be generated on-the-fly as needed. Therefore, this paper presents the custom hardware design and implementation of multiplicative inverse value generator using logarithm method specifically for AES algorithm. The logarithm method benefits the usage of antilog and log values in obtaining the multiplicative inverse value. The EDA tools as Intel Quartus Prime, Synopsys Design Compiler and IC Compiler are used to perform functional simulation, on synthesis analysis and block-level implementation. Detailed comparison is made between this work and previous implementation. The newly designed multiplicative inverse value generator has achieved the improvement on speed and area as compared to previous implementation. The area of the design is reduced around 8.5% with current improvement of 63.091 μm2, while the speed has increased to 2.54 ns with a positive slack of 0.11 ns, which is shorter than the previous implementation. The new design also outreached the performance of the common LUT-based design.
  • Publication
    Hardware Design of Combinational 128-bit Camellia Symmetric Cipher using 0.18µm Technology
    ( 2022)
    Chawalit Udom Sak
    ;
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    Camellia is another symmetric key block cipher with a 128-bit block size and key sizes of 128, 192, and 256 bits. As the hardware version of cipher implementation is getting popular, the Camellia hardware design should be constantly improved in terms of performance. The key aim of this research is to design and implement the improved version of Camellia cipher using custom-based approach based on 0.18µm technology. The new hardware Camellia design is synthesized using timing, area and power constraints to achieve less area, less power and high-speed design. Finally the results are been compared and analyzed with previous implementation in terms of performance parameters. The design is described using Verilog HDL and been verified using functional simulation from the Modelsim-Intel FPGA, while Synopsys had been utilized for synthesis process. Based on the generated synthesis reports, the total area consumed by the design on ASIC platform is 1294.11-unit area with a total cell area of 1176.25-unit area, while the total power consumption is 0.1245mW, and an increased speed of more than 80% as compared to previous design. In conclusion, this design had achieved better performance compared to previous design.
  • Publication
    Crypto-Core Design using Camellia Cipher
    ( 2021-03-01)
    Wei Ci C.
    ;
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Razaidi Hussin
    ;
    Mohd Nazrin Md Isa
    ;
    Basir M.S.S.M.
    Camellia cipher is another symmetric block cipher which allows the encryption and decryption process to share the same key. The cipher permits a 128-bits input data with three different key size: 128, 192 and 256 bits. This paper presents two hardware design approach of Camellia cipher, which are FPGA and custom-based design approach. These approaches utilized design softwares of Altera Quartus II with device family of Cyclone II and Synopsys Design Compiler. The performance of Camellia crypto-core design is then been evaluated based on the implementation platform in terms of speed, area and power. With an equal base of 50MHz of clock frequency, custom-based design is found more efficient than FPGA-based design due to the execution time achieved with 8.46ns, which is faster than the latter that consumed double the time with 16.075ns. The custom-based design achieved 15.13 Gbps of throughput. Besides, the power consumption of custom-based design is 1.3519 mW which is lower than the FPGA-based design. In a nutshell, the design has successfully done as it achieved expected encryption and decryption outcomes with acceptable performance.
  • Publication
    Image Processing for Paddy Disease Detection Using K-Means Clustering and GLCM Algorithm
    ( 2021-12-01)
    Ahmad Effendi A.F.A.
    ;
    Mohd Nazrin Md Isa
    ;
    Ahmad M.I.
    ;
    Che Husin M.F.
    ;
    Siti Zarina Md Naziri
    The traditional human-based visual quality inspection approach in agriculture is unreliable and uneven due to various variables, including human errors. In addition to the lengthy processing durations, the traditional method necessitates plant disease diagnostic experts. On the other hand, existing image processing approaches in agriculture produce low-quality output images despite having a faster computation time. As a result, a more comprehensive set of image processing algorithms was used to improve plant disease detection. This research aims to develop an efficient method for detecting leaf diseases using image processing techniques. In this work, identifying paddy diseases based on their leaves involved a number of image-processing stages, including image pre-processing, image segmentation, feature extraction, and eventually paddy leaf disease classification. The proposed work targeted the segmentation step, whereby an input image is segmented using the K-Means clustering with image scaling and colour conversion technique in the pre-processing stage. In addition, the Gray Level Co-occurrence Matrix technique (GLCM) is used to extract the features of the segmented images, which are used to compare the images for classification. The experiment is implemented in MATLAB software and PC hardware to process infected paddy leaf images. Results have shown that K-Means Clustering and GLCM are capable without using the hybrid algorithm on each image processing phase and are suitable for paddy disease detection.