Rizalafande Che Ismail
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Preferred name
Rizalafande Che Ismail
Official Name
Rizalafande, Che Ismail
Alternative Name
Ismail, Rizalafande C.
Rizalafande, Che Ismail
Chesmail, R.
Ismail, R. C.
Che Ismail, Rizalafande
Ismail, Rizalafande Che
Ismail, R. Che
Main Affiliation
Scopus Author ID
22634128600

Research Output
Now showing 1 - 10 of 23
  • Publication
    An implementation of Short Time Fourier Transform for Harmonic Signal Detection
    ( 2021-03-01)
    Basir M.S.S.M.
    ;
    Rizalafande Che Ismail
    ;
    Yusof K.H.
    ;
    Katim N.I.A.
    ;
    Mohd Nazrin Md Isa
    ;
    Siti Zarina Md Naziri
    Power electronic components has the tendency to induce a non-linear signal called harmonic distortion. Without proper monitoring tools, harmonic distortion can harm sensitive electronic equipment, and in worse case scenarios, may lead to unreliable operation of controller and misalignment of motoring unit. This matter can be compromised by taking safety precaution, by identifying the level of harmonic rise in the electrical system. This paper presents analysis on different characteristics of harmonic signal using frequency distribution technique, namely Fourier transform (FT), and proposal of time-frequency distribution (TFD) technique, which is a short time Fourier transform (STFT). The novelty of utilizing STFT is the analyzed signal is represented in both time and frequency marginals, hence providing extra information of the spectral over the time. Simulation was carried out using MATLAB, by means the results consisting of the magnitude of multi-frequency components signal were represented in time-frequency representation (TFR). From the TFR, parameters such as instantaneous RMS fundamental voltage, V1RMS(t), instantaneous RMS voltage, VRMS(t), instantaneous total waveform distortion, VTWD(t), instantaneous total harmonic distortion, VTHD(t) and instantaneous total nonharmonic distortion, VTnHD(t) had been extracted. The performance of different harmonic signals such as normal, single-level harmonic, multi-level harmonic, short duration harmonic and interharmonic had been analyzed. The performance based on absolute percentage error (APE) index indicated average of 93% of correctness using 256 window length in STFT measurement.
  • Publication
    Less memory and high accuracy logarithmic number system architecture for arithmetic operations
    ( 2021-09-01)
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    Interpolation is another important procedure for logarithmic number system (LNS) addition and subtraction. As a medium of approximation, the interpolation procedure has an urgent need to be enhanced to increase the accuracy of the operation results. Previously, most of the interpolation procedures utilized the first degree interpolators with special error correction procedure which aim to eliminate additional embedded multiplications. However, the interpolation procedure for this research was elevated up to a second degree interpolation. Proper design process, investigation, and analysis were done for these interpolation configurations in positive region by standardizing the same co-transformation procedure, which is the extended range, second order co-transformation. Newton divided differences turned out to be the best interpolator for second degree implementation of LNS addition and subtraction, with the best-achieved BTFP rate of +0.4514 and reduction of memory consumption compared to the same arithmetic used in european logarithmic microprocessor (ELM) up to 51%.
  • Publication
    An Analysis of Interpolation Implementation for LNS Addition and Subtraction Function in Positive Region
    ( 2016)
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Ali Yeon Md Shakaff
    Interpolation is among of the most popular approach used in approximating the values in logarithmic number system (LNS) arithmetic design. This method that often combines with lookup tables (LUTs) manages to produce efficient LNS design in area, latency and accuracy. Current research proves that the combination of interpolators with co-transformation in LNS subtraction had shown extreme improvements in terms of speed and area, which is comparable to floating point (FLP) performance. Taking the advantage, this research had been conducted to analyze the implementation of these three interpolators, which are Taylor, Lagrange and modified Lagrange, in a 32-bit environment of the LNS addition and subtraction procedures with the first-order co-transformation in positive region. The designs were analyzed in two categories, which are the accuracy towards FLP and the total memory consumption. The best interpolator was selected based on the most optimum area consumption design with manageable accuracy in FLP limit. The outcome of this analysis could benefit further improvements in LNS design.
  • Publication
    Development of Soil Electrical Conductivity (EC) Sensing System in Paddy Field
    ( 2021-03-01)
    Othaman N.N.C.
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    ;
    Rizalafande Che Ismail
    ;
    Siti Zarina Md Naziri
    ;
    Sohiful Anuar Zainol Murad
    ;
    Azizi Harun
    ;
    Muhammad Imran Ahmad
    The amount of fertilisers affects electrical conductivity (EC), and it is one of the major causes of the paddy yield decrease. The overuse of fertilisers can lead to environmental pollution and contamination. This study designed to develop soil electrical conductivity (EC) sensing system in the paddy field using the smart farming application. In this work, the study conducted in Kampung Ladang, Kuala Perlis, and the soil samples collected from a random location at two different depths from the paddy field. The EC value for the developed system was near the calibration solutions (12880µS and 150000µS) and directly proportional to the temperature. From the laboratory soil results, the EC values of the soils were higher with fertiliser. However, the EC values for 0-10cm soil depth were higher than 10-20cm soil depth. The soil EC is inversely proportional to the depth of soil and directly proportional to the amount of nutrients. It observed that the soil EC is linearly related to the amount of nutrients and temperature. The EC value decreases with the increase of soil depth displays a low amount of salts in the deep soil, while, increases with the increase of temperature indicates high current flow.
  • Publication
    Face Recognition and Identification using Deep Learning Approach
    ( 2021)
    KH Teoh
    ;
    Rizalafande Che Ismail
    ;
    Siti Zarina Md Naziri
    ;
    Razaidi Hussin
    ;
    Mohd Nazrin Md Isa
    ;
    Muhammad Sufyan Safwan Basir
    Human face is the significant characteristic to identify a person. Everyone has their own unique face even for twins. Thus, a face recognition and identification are required to distinguish each other. A face recognition system is the verification system to find a person’s identity through biometric method. Face recognition has become a popular method nowadays in many applications such as phone unlock system, criminal identification and even home security system. This system is more secure as it does not need any dependencies such as key and card but only facial image is needed. Generally, human recognition system involves 2 phases which are face detection and face identification. This paper describes the concept on how to design and develop a face recognition system through deep learning using OpenCV in python. Deep learning is an approach to perform the face recognition and seems to be an adequate method to carry out face recognition due to its high accuracy. Experimental results are provided to demonstrate the accuracy of the proposed face recognition system.
  • Publication
    Analysis of FXP adders and multipliers for speed- and area-efficient LNS arithmetic unit
    ( 2014)
    Rizalafande Che Ismail
    ;
    Siti Zarina Md Naziri
    ;
    Sohiful Anuar Zainol Murad
    ;
    J. N. Coleman
    This paper portrays the selection of hardware unit architectures to be implemented in the new LNS based on a 32bit system. The implementations of the LNS multiply and divide only require a FXP adder, while the LNS addition and subtraction function comprised of several memories, FXP adders and multipliers together with other supporting logics. Thus, in choosing the best FXP adders and multipliers, each of the arithmetic is functionally verified and synthesised using Synopsys Design Compiler in Faraday 0.18 μm CMOS technology based on a 32-bit system. Two types of performance measurement, which are the worst-case delay and the silicon area, are chosen as the evaluation arguments. From conducted analytical studies, the CLA/CSLA adder and Booth recoded with Wallace tree multiplier were the best FXP adder and multiplier blocks to be applied in the system since they were the fastest designs. Using these blocks, the synthesis of the LNS system produced an approximately 7.10 ns of critical delay for addition and subtraction, and solely 1.16 ns for multiplication and division. The total area for a complete LNS architecture was 599,871 μm2, in which 65% the size of previously designed LNS architecture of ELM. © 2014 IEEE.
  • Publication
    Design of Multiplicative Inverse Value Generator using Logarithm Method for AES Algorithm
    ( 2020-12-14)
    Yen, Goh Yie
    ;
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    Advanced Encryption Standard (AES) algorithm is one of the most widely used symmetric block cipher that is utilized in data protection through symmetric cryptography algorithm, as it offers high efficiency and ability in securing information. In AES, the SubByte/InvSubByte transformation costs an amount of memories for the lookup tables (LUT) that leads to area usage in hardware. As per mathematical equations, the SubByte/InvSubByte is able to share the same resource which is the multiplicative inverse value table. Instead of using LUTs, the multiplicative inverse values can be generated on-the-fly as needed. Therefore, this paper presents the custom hardware design and implementation of multiplicative inverse value generator using logarithm method specifically for AES algorithm. The logarithm method benefits the usage of antilog and log values in obtaining the multiplicative inverse value. The EDA tools as Intel Quartus Prime, Synopsys Design Compiler and IC Compiler are used to perform functional simulation, on synthesis analysis and block-level implementation. Detailed comparison is made between this work and previous implementation. The newly designed multiplicative inverse value generator has achieved the improvement on speed and area as compared to previous implementation. The area of the design is reduced around 8.5% with current improvement of 63.091 μm2, while the speed has increased to 2.54 ns with a positive slack of 0.11 ns, which is shorter than the previous implementation. The new design also outreached the performance of the common LUT-based design.
  • Publication
    Hardware Design of Combinational 128-bit Camellia Symmetric Cipher using 0.18µm Technology
    ( 2022)
    Chawalit Udom Sak
    ;
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    Camellia is another symmetric key block cipher with a 128-bit block size and key sizes of 128, 192, and 256 bits. As the hardware version of cipher implementation is getting popular, the Camellia hardware design should be constantly improved in terms of performance. The key aim of this research is to design and implement the improved version of Camellia cipher using custom-based approach based on 0.18µm technology. The new hardware Camellia design is synthesized using timing, area and power constraints to achieve less area, less power and high-speed design. Finally the results are been compared and analyzed with previous implementation in terms of performance parameters. The design is described using Verilog HDL and been verified using functional simulation from the Modelsim-Intel FPGA, while Synopsys had been utilized for synthesis process. Based on the generated synthesis reports, the total area consumed by the design on ASIC platform is 1294.11-unit area with a total cell area of 1176.25-unit area, while the total power consumption is 0.1245mW, and an increased speed of more than 80% as compared to previous design. In conclusion, this design had achieved better performance compared to previous design.
  • Publication
    Implementation of LNS addition and subtraction function with co-transformation in positive and negative region: A comparative analysis
    ( 2016)
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Ali Yeon Md Shakaff
    The European Logarithmic Microprocessor (ELM) had been an outstanding breakthrough in logarithmic number system (LNS) research history. The processor successfully reaches the par ability of floating-point (FLP) processor with its rapid and accurate design towards FLP. The design was able to improve the LNS addition and subtraction procedure, which are the drawbacks of any implementation of LNS arithmetic. ELM's subtraction operation had adopted a unique approach, which is the first-order co-transformation to overcome the singularity-to-zero issue of the non-linear function in negative region. Therefore, this research had been introduced to extensively compare and analyze the ELM-based addition and subtraction procedures with the same co-transformation technique implemented in positive region. In achieving this, two aspects are considered, which are the accuracy towards FLP and the memory consumption of both procedures in both regions. Conclusively, the exact ELM-based implementation in positive region of both operations could be realized and achieved comparable accuracy and memory area with a slight modification of the operation procedure. The outcome of this analysis could benefit further investigation of optimizing the LNS design for hardware implementation.
  • Publication
    Crypto-Core Design using Camellia Cipher
    ( 2021-03-01)
    Wei Ci C.
    ;
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Razaidi Hussin
    ;
    Mohd Nazrin Md Isa
    ;
    Basir M.S.S.M.
    Camellia cipher is another symmetric block cipher which allows the encryption and decryption process to share the same key. The cipher permits a 128-bits input data with three different key size: 128, 192 and 256 bits. This paper presents two hardware design approach of Camellia cipher, which are FPGA and custom-based design approach. These approaches utilized design softwares of Altera Quartus II with device family of Cyclone II and Synopsys Design Compiler. The performance of Camellia crypto-core design is then been evaluated based on the implementation platform in terms of speed, area and power. With an equal base of 50MHz of clock frequency, custom-based design is found more efficient than FPGA-based design due to the execution time achieved with 8.46ns, which is faster than the latter that consumed double the time with 16.075ns. The custom-based design achieved 15.13 Gbps of throughput. Besides, the power consumption of custom-based design is 1.3519 mW which is lower than the FPGA-based design. In a nutshell, the design has successfully done as it achieved expected encryption and decryption outcomes with acceptable performance.