Ramzan Mat Ayub
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Ramzan Mat Ayub
Official Name
Ramzan, Mat Ayub
Alternative Name
Mat Ayub, R.
Ayub, R. Mat
Ayub, R. M.
Ayub, Rm
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Scopus Author ID
21741780500

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  • Publication
    Lectin bioreceptor approach in capacitive biosensor for prostate-specific membrane antigen detection in diagnosing prostate cancer
    ( 2021-03-01)
    Subramani I.G.
    ;
    Ramzan Mat Ayub
    ;
    Subash Chandra Bose Gopinath
    ;
    Perumal V.
    ;
    Mohamad Faris Mohamad Fathil
    ;
    Mohd Khairuddin Md Arshad
    This research reports a new approach with lectin-based capacitive non-faradaic biosensor for the detection of prostate-specific membrane antigen (PSMA) as a promising diagnostic marker for determining prostate cancer. PSMA expression is significantly higher in malign hyperplasia, thus can be effectively employed to discriminate other benign prostatic diseases. Herein, the aluminium interdigitated electrode was fabricated and modified by a linker, 2-mercaptoacetate to form the self-assembled monolayer. Gold nanoparticles were used as a signal amplifier and supported the conjugation of Concanavalin A, for efficient capacitive sensing of PSMA. Scanning electron microscope observation effectively captured the surface modification on the aluminium surface by revealing the specific adherence of gold nanoparticles with Concanavalin A. Moreover, the successful surface modification was further validated by atomic force microscopy, Fourier transforms infrared spectroscopy, and X-ray photoelectron spectroscopy. The interaction analysis of Concanavalin A with PSMA by capacitive non-faradaic measurement exhibited a linear detection range from 10 pM to 100 nM and attained the detection limit and sensitivity of 10 pM and 1.65 nF/pM respectively as the comparable performance to the current sensing strategies. Furthermore, the fabrication and quantification of PSMA as demonstrated here are relatively simple and can be employed for the straightforward detection of other biomarkers.
  • Publication
    Design and simulation of Cylindrical Stacked Silicon Nanowire (SiNW) field-effect transistors
    (IEEE, 2023-12)
    H’ng Chee Chang
    ;
    Mohd Khairuddin Md Arshad
    ;
    Mohamad Faris Mohamad Fathil
    ;
    Mohammad Nuzaihan Md Nor
    ;
    Subash Chandra Bose Gopinath
    ;
    Ramzan Mat Ayub
    In continuous effort to increase the current drive without sacrificing the off current and better off gate control on the channel, the MOSFET devices have advanced from classical, planar, single-gate and three-dimensional devices with multi-gate structures. Recently, multi-bridge-channel technology has become a feasible solution beyond FinFET multi-gate structure. In this work, we design Gate-All-Around (GAA) based on silicon nanowire. Numerical simulation based Silvaco Device tools has been used to design multiple number of cylindrical nanowires, then followed by different channel diameter, consisting of 20, 30 and 40 nm. The devices are the characterized on transconductance, threshold voltage, DIBL and subthreshold slope. The simulation results indicate that the device performance is best at a nanowire diameter of 20 nm due to improved gate control over charge distribution. Regarding the number of nanowires, the voltage performance is not significantly affected by Nnw =1 or higher. However, higher numbers of nanowires, such as Nnw = 3, demonstrate improved drain current and transconductance.
  • Publication
    Numerical simulation on the impact of back gate voltage in thin body and thin buried oxide of silicon on insulator (SOI) MOSFETs
    ( 2023-10)
    K.Y Koay
    ;
    Mohamad Faris Mohamad Fathil
    ;
    Mohammad Nuzaihan Md Nor
    ;
    Ramzan Mat Ayub
    ;
    Mohd Khairuddin Md Arshad
    Silicon-on-Insulator (SOI) technology provides a solution for controlling Short-Channel Effects (SCEs) and enhancing the performance of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). However, scaling down SOI MOSFETs to a nanometer scale does not necessarily yield further scaling benefits. Introducing multiple gates, such as a double gate configuration, can effectively mitigate SCEs. Nonetheless, fabricating a flawless double gate structure is an exceedingly challenging endeavor that remains unrealized. The adoption of a back gate bias, with an asymmetrical thickness arrangement between the front and back gates, mimicking the behavior of a double gate, offers an alternative approach. This approach has the potential to modify the electrical characteristics of the device, thus potentially leading to improved control over SCEs. In this study, we employed 2D simulations using Atlas to investigate the influence of back gate biases, namely, -2.0 V, 0 V, and 2.0 V on a 10 nm silicon thickness at the top and a 20 nm buried oxide thickness for n-channel MOSFETs. We focused on key parameters, including threshold voltage (VTh), Drain Induced Barrier Lowering (DIBL), and Subthreshold Swing (SS). The results demonstrate that a negative back gate bias is the most favorable configuration, as it yields superior performance. This translates into more effectively controlled SCEs across all the parameters of interest.
      1  7
  • Publication
    Electrical simulation on silicon nanowire field-effect transistor biosensor at different substrate-gate voltage bias conditions for charge detection
    ( 2022-12)
    X.Y. Teoh
    ;
    Mohamad Faris Mohamad Fathil
    ;
    Y.M.Tan
    ;
    Norhayati Sabani
    ;
    Mohammad Nuzaihan Md Nor
    ;
    Mohd Khairuddin Md Arshad
    ;
    Ruslinda A. Rahim
    ;
    Nur Hamidah Abdul Halim
    ;
    Ramzan Mat Ayub
    ;
    Uda Hashim
    ;
    M.M. Ibrahim
    In this work, the impact of different substrate-gate voltage bias conditions (below and above the device threshold voltage) on current-voltage characteristics and sensitivity of a silicon nanowire field-effect transistor (SiNW-FET) biosensor was investigated. A 3-dimensional device structure with n-type SiNW channel and a substrate gate electrode was designed and electrically simulated In the Silvaco ATLAS. Next, the SiNW channel was covered with a range of interface charge density to mimic the charged target biomolecule captured by the device. The outcome was translated into a drain current versus interface charge semi-log graph and the device sensitivity was calculated using the linear regression curve’s slope of the plotted data. The device’s electrical characteristic shown higher generation of output drain current values with the increase of negative substrate-gate voltage bias due to the hole carriers’ accumulation that forms a conduction channel in the SiNW. Application of higher negative interface charge density increased the change in drain current, with the device biased with higher substrate-gate voltage shows more significant change in drain current. The device sensitivity increased when biased with higher substrate-gate voltage with highest sensitivity is 75.12 nA/dec at substrate-gate voltage bias of –1.00 V.
      3  62
  • Publication
    FET with underlap structure for biosensing applications
    ( 2018-01)
    Claris C. J. W
    ;
    Mohd Khairuddin Md Arshad
    ;
    C. Ibau
    ;
    Ramzan Mat Ayub
    ;
    Mohamad Faris Mohamad Fathil
    ;
    Norhaimi W. M. W.
    This paper presents the numerical simulation of an underlap field effect transistor (FET) device architecture on silicon‐on‐insulator (SOI) substrate for biosensing applications. By using the Silvaco ATLAS device simulator, this work is aimed to elucidate the effects of the different gate lengths, the presence of interface charge on the underlap sensing region, and also the effects of different gate biases (i.e. singlegate biasing, synchronous doublegate biasing and asynchronous doublegate biasing) on the magnitude of drain current (ID) of the simulated device. It is found that shorter gate length with the positive charges (on the n‐p‐n structure), at the sensing channel area increased the electron concentration at the channel and substrate/buried oxide interface. In asynchronous doublegate with a +3V of back‐gate supply and synchronous double‐gate, both increased the ID at different magnitude level and off‐current. Thus, depending on the biomolecule charges, the substrate biasing can be altered to improve the device’s sensitivity.
      17  2
  • Publication
    Numerical Simulation on the Impact of Back Gate Voltage in Thin Body and Thin Buried Oxide of Silicon on Insulator (SOI) MOSFETs
    ( 2023-10-01)
    Koay K.Y.
    ;
    Mohamad Faris Mohamad Fathil
    ;
    Mohammad Nuzaihan Md Nor
    ;
    Ramzan Mat Ayub
    ;
    Mohd Khairuddin Md Arshad
    Silicon-on-Insulator (SOI) technology provides a solution for controlling Short-Channel Effects (SCEs) and enhancing the performance of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). However, scaling down SOI MOSFETs to a nanometer scale does not necessarily yield further scaling benefits. Introducing multiple gates, such as a double gate configuration, can effectively mitigate SCEs. Nonetheless, fabricating a flawless double gate structure is an exceedingly challenging endeavor that remains unrealized. The adoption of a back gate bias, with an asymmetrical thickness arrangement between the front and back gates, mimicking the behavior of a double gate, offers an alternative approach. This approach has the potential to modify the electrical characteristics of the device, thus potentially leading to improved control over SCEs. In this study, we employed 2D simulations using Atlas to investigate the influence of back gate biases, namely,-2.0 V, 0 V, and 2.0 V on a 10 nm silicon thickness at the top and a 20 nm buried oxide thickness for n-channel MOSFETs. We focused on key parameters, including threshold voltage (VTh), Drain Induced Barrier Lowering (DIBL), and Subthreshold Swing (SS). The results demonstrate that a negative back gate bias is the most favorable configuration, as it yields superior performance. This translates into more effectively controlled SCEs across all the parameters of interest.
      35  1