This paper presents the numerical simulation of an underlap field effect transistor (FET) device architecture on silicon‐on‐insulator (SOI) substrate for biosensing applications. By using the Silvaco ATLAS device simulator, this work is aimed to elucidate the effects of the different gate lengths, the presence of interface charge on the underlap sensing region, and also the effects of different gate biases (i.e. singlegate biasing, synchronous doublegate biasing and asynchronous doublegate biasing) on the magnitude of drain current (ID) of the simulated device. It is found that shorter gate length with the positive charges (on the n‐p‐n structure), at the sensing channel area increased the electron concentration at the channel and substrate/buried oxide interface. In asynchronous doublegate with a +3V of back‐gate supply and synchronous double‐gate, both increased the ID at different magnitude level and off‐current. Thus, depending on the biomolecule charges, the substrate biasing can be altered to improve the device’s sensitivity.
