Theses & Dissertations

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  • Publication
    Classification of binary insect images using fuzzy and gaussian artmap neural networks
    ( 2006)
    Shahrul Nizam Yaakob
    Object recognition and classification is an essential routine in our daily lives. Our eyes act as a camera capturing the image of particular object and sending it to the brain to be recognized. Thus, the eye vision system inspires researchers to create machine vision systems. As a significant part of the machine vision system, this research focused on two (2) important phases of the system; feature extraction and classification. As for the feature extraction six (6) different types of moment invariant techniques namely Geometric moment invariant (GMI), United moment invariant (UMI), Zernike moment invariant (ZMI), Legendre moment invariant (LMI), Tchebichefmoment invariant (I'MI) and Krawtchouk moment invariant (KMI) are used to extract the global shape features of the binary insect images. These features are then channeled to the Fuzzy ARTMAP (FAM) and Gaussian ARTMAP( GAM )neural network to be classified and recognized. In the GAM neural network, a gamma threshold is proposed to find the optimal value for gamma parameter acting as the initial value for a Gaussian distribution in the training phase. It is found that KMI is the best technique for features extraction of the global shape information of the insect images as compared to GMI, UM!, ZM!, LMI and TMI. The finding is based on the lowest value of Total Min Absolute Error (I'PMAE) (0.03%-1.01). The training and testing method for both neural networks is based on 4- folds cross validation technique. It is also found that the performance of F AM neural network is influenced by the types of normalization technique utilized. The Improved Linear Scaling (ILS) normalization technique generated the highest classification rate by the F AM neural network when compared to Unit Range (UR) and Improved Unit Range (IUR). It is further found that GAM neural network is a better insect classification technique when compared to F AM neural network producing the classification accuracy up to 99.58% whereby the classification accuracy of FAM neural network is 82%.
  • Publication
    Design, simulation and process development for Sol Single-Electron Transistor (SET) fabrication
    ( 2006)
    Amiza Rasmi
    Single-electron transistor (SET) is one of the promising nanotechnologies and distinguished by a very small device size and low power dissipation. This project explains the SET mask design, SET process flow development, and SET process and device simulation. The SET mask design consists of four level masks namely source and drain mask, polysilicon gate mask, contact mask, and metal mask. These masks were designed in nanometer (10-9 m) size using ELPHY Quantum GDS II Editor Software. The source and drain mask is connected by a nanowire placed between source and drain regions. The nanowire is designed with dimension of approximately 100 nm long and 10 nm wide. The process flow which includes the detailed parameters is developed for SET process and device simulation. This process flow consists of ten process modules include wafer cleaning process, material deposition, source/drain and nanowire formation , thermal oxidation, polysilicon deposition, polysilicon gate formation, source/drain implantation, contact formation, metal deposition and formation, and finally annealing and alloying process. The Synopsys TCAD simulation tools are utilized in SET process and device simulation work. The process and device simulation result shows that the single-electron transistor design with a 100 nm length and 10 nm width of the nanowire is working at room temperature (300 K) operation with a capacitance 0.4297 x 10-18F and a charging energy 186.4 meV.
      2  8
  • Publication
    Database encryption for a web-based claims system
    ( 2007)
    Syed Zulkarnain Syed Idrus
    The main purpose of this study is to develop a computer system for UniMAP staff to make claims via electronic media. The system development is based on the Treasury Circulars by the Ministry of Finance, Malaysia as well as other circulars related to it. Other important particulars had been built into the system such as salary, grade, entitlement and others. Another additional feature included is the automatic calculations. This system can also be equipped with a security tool to prevent hackers or unauthorised persons, which can be selected from the results of the security analysis. There are three categories of user involved in the development of the system. They are the Claimant, Responsibility Centre and Bursary Department. The Responsibility Centre consists of all administrative departments as well as centres of study from where the budget allocation is acquired. The development of the system begins by designing of the Process Flow Diagrams showing the steps or procedures that need to be followed in sequence respectively. All the three categories of users must follow their flow of the diagrams. Process flow is a flow that determines the movements of the forms from the moment they are submitted up to the stage where payments will be made. This process is to be followed by the designing the Data Flow Diagram and then the Database. The former specifies how the data will flow in the system, whereas the latter is for data storage where all data are kept such as login identifications, passwords, staff personal particulars, entitlements etc. The development of the Database comes in four forms namely Entity-Relationship Diagram, Hierarchical Diagram, Relational Database Diagram and Data Dictionary. Out of twenty encryption algorithms that are available in the Dynamic-Link Library (DLL), only five have been selected to go through and perform analysis for comparison in terms of its performance and compatibility with the developed system. Since this system is Web-based, staff can make claims anywhere, anytime and at any locations. This method can overcome not only human errors but also more efficient, fast and accurate. Therefore, this system can also save time, effort, and administrative costs. In this study, Active Server Pages (ASP) has been chosen to make the calculation and also to generate reports. After the system has been developed, a test was conducted using forms that have been simulated manually. The purpose is to enable the researcher to make comparison with the ones made using the developed system in order to detect errors or flaws from the manual simulation in the system. Testing was also done on the encryption algorithms and Web browsers selected by increasing both the text length size and key length size and observed its performances. Having noted its response times, an analysis was made in order to determine which encryption algorithms’ and Web browsers’ performances were most suited for the developed system and considered the best, which is lower and able to sustain its response times. The results of this study have shown that this system is able to detect all human errors in the traditional manual claim system, in which claimants have made some mistakes. On the other hand, the analysis of encryption algorithms with Web browsers, the results have shown that Twofish algorithm is best suited to the system that has been developed using ASP Web programming language on Internet Explorer. Hence, it is emphatic that all objectives that had been set at the beginning of this research have been met.
  • Publication
    Object detection using image processing techniques: coconut as a case study
    ( 2007)
    Haniza Yazid
    The use of computers to analyze images has many potential but, the variability of the objects makes it a challenging task. In this thesis, the main idea is to detect an object (coconut) from an image. Several techniques have been utilized namely, the separable filter, Circular Hough Transform (CHT), chord intersection and moment invariant. Before applying these techniques, the preprocessing and image segmentation steps need to be performed in priori. Histogram equalization is utilized in preprocessing step meanwhile edge detection and morphological filtering have been employed in image segmentation step. Single object has been experimented to evaluate the two (2) techniques, CHT and the chord intersection. Based on the results obtained from single object detection, the CRT achieves higher percentage, 87.5% than chord intersection technique, 85%. For multiple objects detection, the CHT technique has been used and the highest detection for the first object is 87.5% followed by 92.5% for the second object, 77.5% for the third object and the last object is 67.5%. The moment invariant technique has been used to extract the shape of the object and detect its presence. From 50 images that have been experimented, 90% show positive result. This research can be adopted for climbing robotic system that can automatically pluck the coconut from a tree. Using image processing techniques, the gripping process will be easier and convenient than manual plucking.
  • Publication
    Fabrication and characterization of ultra thin Si0₂ for nano devices: surface morphology and electrical study
    ( 2007)
    Mohd Faiz Aizad Abdul Fatah
    The aim of this research is to fabricate and characterize (optical and electrical) an ultra thin silicon dioxide for sub nano devices. In this research, dry oxidation method using high temperature furnace is chosen to fabricate a thin layer of oxide below 30Angstroms. There are three level of temperature used. that is 7S0, 800 and 8S(/C. The wqfers were grown in 0.333 litre/min. 0,667 liter/min and 1.00 literlmin oxygen flow rate with variation in growth time 1, 2 and 3 minutes. Thicknesses were obtained using ellipsometer and the surface topography and were achieved using atomic force microscope (UM). Parameters and data has been interpreted using Taguchi's method. This is to analyze the most affecting factors in producing an ultra thin silicon dioxide. Taguchi's method were able to predict the thicknesses for each combination of parameters. Results show that the temperature is the most effecting factor that effects the growth of oxide. Results also show that oxygen flow rates do have an influence to the thicknesses and surface properties. A higher amount of flow rate (illmin) will increase the oxide thickness and also will create a smooth oxide surface. There are also results of a high frequency CV and IV techniques were employed as for the devices electrical characterizations. The CV results shows that there is a shift in VFB for all the wafers and IV shows that breakdown occurs at 1 MV/cm.
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  • Publication
    Fabrication of silicon nanowires using Scanning Electron Microscope based Electron Beam Lithography method
    ( 2007)
    Mohammad Nuzaihan Md Nor
    Nanowires is a new class of materials that have attracted attention and great research interest in the last few years because of their potential applications in nanotechnology such as nanoelectronic, nanomechanical and biomedical engineering. Fabrication of Nanowires is one of the great challenges today. Conventional lithography methods are not capable to produce Nanowires and even with advance nanolithography sizes below 100 nm may not easily be achieved. The goal of this research work is to form and produce very small nanowires using a Top-Down Nanofabrication Method which involved Scanning Electron Microscope (SEM) based Electron Beam Lithography (EBL) method. Initially, the Top-Down Nanofabrication Method based on EBL was the design of the Nanowires Pattern Design (NPD). The NPD has been done by software called RAITH ELPHY Quantum GDSII Editor. The software package provides all the features needed to produce micro and nano scale structures starting from a structure design, post processing and design modification. The NPD is designed in various nanowires scale size from 100 nm down to 20 nm. Next, the nanofabrication process flow development which consists of the detailed parameters and recipes are developed for nanowires formation. Two (2) types of resist masks and three (3) types of nanowires are involved in the process flow development. The Resist Masks consist of PMMA Resist Mask and ma-N 2400 Series Resist Mask. It is used as a mask material or etches mask during Silicon Dioxide etching process. Fabrication of Nanowires is the main focus in this research work which consists of SiO2, Si, a-Si Nanowires. SiO2 Nanowires is used as insulation and hard mask for silicon etching in order to form Si Nanowires. Si Nanowires and a-Si Nanowires are widely used as semiconducting nanowires and has great potential in nanoelectronic devices. In order to produce very small nanowires, the dimensions, developments, etch profiles of nanowires and size-reduction by thermal oxidation was investigated. Finally, the combination on Top-Down Nanofabrication Method and size-reduction has resulted in successful reduction of Si Nanowires reduced from 100 nm to approximately 20 nm.
      2  3
  • Publication
    Characterization of alignment mark to obtain reliable alignment performance in advanced lithography
    ( 2007)
    Normah Ahmad
    The continued downscaling of semiconductor fabrication has imposed increasingly tighter overlay tolerances. Such tight tolerances will require very high performance in alignment. Hence, the objective of this research to establish characterization process for alignment evaluation and to determine the robust alignment strategy for via 1 and metal 1 masking layers. This research covers four aspects, namely to find robust alignment mark for Metal 1 and Vial layer, alignment performance comparison between via mark and metal mark, alignment mark feature size effect on alignment signal, and to evaluate the new metal alignment mark performance. In order to achieve these objectives, a fractional factorial experiment with 4 parameters variation (tungsten thickness, over polish time, aluminum thickness, and final oxide thickness) and one duplicate was developed. Fifteen alignment Mark types were evaluated. Based from the characterization experiment, B2 mark with highest capability score (4979) and weighted Cpk score (75.16) is the 11I0St robust alignment mark for Metal 1 layer. A3 is the most robust alignment mark for Via 1 layer. A3 mark gives the highest total score in weighted average capability analysis (2173.52) and Cpk analysis (2800). Based on this work, contact mark is more sensitive to process variation as it pattern formation involved 6 processing steps compared to 3 steps for metal mark. For via //lark, big mark size (more than 2.6 f.1m) gives bad alignment signal quality compared to the smaller feature size. Regardless of mark size, alignment signal generates by metal mark gives comparable results. Two types of new metal alignment mark designs (B8 and B9) were evaluated in this experiment. The results were compared with standard metal mark (B6) and standard via mark (B4). B8 gives the best overall alignment and overlay performance since it gives the highest total in weighted average analysis (/40.96(alignment) and 53.43 (overlay)). The research findings becomes a baseline for C18 technology alignment process and already implemented in our production line.
      2  4
  • Publication
    Temperature cycling reliability test for a ball grid array (BGA) package using finite element analysis (FEA)
    ( 2008)
    Muhammad Nubli Zulkifli
    Thermal cycling test is one of the reliability test that has been used to evaluate the reliability of the solder joint interconnect in ball grid array (BGA) package. The purpose of thermal cycling test is to characterize thermomechanical failure mechanism on microelectronics package. This research utilizes the computer capability to run the thermal cycling test by using finite element analysis (FEA). FEA of thermal cycling test is done by using ANSYS™ finite element software. Quarter symmetry BGA package model is built parametrically by using APDL (ANSYS™ Parametric Design Language and Macros). Two types of analyses are used to evaluate the reliability performance of solder joints in BGA package, namely the physics based analysis and the statistical based analysis. Darveaux’s energy based fatigue model is used as the constitutive equation for solder. One of the temperature cycling conditions namely, G based on JEDEC JESD22-A104 standard is used throughout the finite element analysis. The effect of different temperature cycling condition is studied by applying different value of dwell times and ramp rates. Two screening design methods namely, Central Composite Design (CCD) and Box-Behnken Matrix Design method are used to isolate the most important factors amongst six design variables such as solder joint standoff height, printed circuited board (PCB) core thickness, PCB core-in-plane Young’s Modulus, PCB core-in-plane coefficient of thermal expansion (CTE), die thickness and mold compound thickness. The optimization process is carried out using response surface methodology (RSM) to predict appropriate variables or factors that have a significant influence on BGA package failure and their interactions. Monte Carlo simulations are used to validate the randomness of the results obtained through CCD and Box-Behnken matrix design based optimization methods. It is observed that changes in ramp rate produce significant effect in solder joint fatigue life rather than changes in dwell time, but the dwell time at high temperature (high dwell) has a negligible contribution to solder joint fatigue life. It is also found that the thickness of the mold has a significant effect on the performance of the solder joint reliability (more than 50 %) as compared to that from other factors. Besides the effect of individual factor, the interaction among factors also changes the solder joint reliability. RSM based on Box-Behnken Matrix design offers the highest characteristic solder joint fatigue life with a value of 2861 cycles or 41.1% enhancement from the initial design set. RSM based on CCD offers the best goodness-of-fit measures over RSM based on Box-Behnken Matrix design. These results show that RSM based on CCD has better accuracy in representing the sample points on response surface.
      2  4
  • Publication
    The effect of Phosphorous implant in converting the enhancement mode transistor into depletion mode transistor
    ( 2008)
    Hazian Mamat
    Metal-Oxide-Semiconductor field effect transistor (MOSFET) forms the basis in most of electronic applications. In certain part of electronic circuitry, there is a requirement to use depletion mode of MOSFET which delivers current at Vg=0V. This type of transistor is normally on unless reverse-polarity Vg is applied to turn it off. In this research, thorough investigations on process parameters that affect the performance of depletion mode transistor have been studied. The study was emphasized on the ion implantation to forms the depletion channel. It is a very crucial process step in creating a successful depletion type MOSFET. To support the study, Design of Experiment (DOE) for ion implantation dose and energy has been implemented in MIMOS fabrication facility. The 0.5um CMOS process technology was used as a baseline to produce n-type depletion mode MOSFET. Besides running the experiment, simulation software (ATHENA and ATLAS) were used in this study to reduce the cost and time of producing experiment wafers. Comparison of experiment test results and simulation output was also discussed in details in this thesis. On the other hand, problems and observations from the experiment were highlighted and discussed too. One of the main issues is on the two-peak point of transconductance curve. According to the experimental results, it can found that phosphorus ion with dose 3.3e12 cm-2 and energy 60 keV used in depletion channel implant should produce good characteristics of depletion mode MOSFET with threshold voltage -0.7 V.
      2  6
  • Publication
    An efficient modified booth multiplier architecture
    ( 2008)
    Razaidi Hussin
    Multiplier plays an important role in today’s compute intensive applications such as computer graphics and digital signal processing. This thesis described the design of an Efficient Modified Booth Multiplier Architecture. With the tradeoff between speed and area, the design of the Modified Booth Multiplier focused on high speed with a moderate increase in area. This was achieved by reducing the critical path delay in the basic element of the multiplier circuit. Multiplication is performed by generating the partial product of Modified Booth Encoding (MBE) and accumulating the entire partial product by an adder or compressor. The research began by examining the available encoding schemes used to generate the partial product and 4:2 compressor that are used to accumulate the partial product. The fastest MBE and the most efficient 4:2 compressor has been used to develop the multiplier. The multiplier performance was improved by adapting various methods such as Simplified Sign Extension (SSE) and a proper tree topology. The SSE method eliminated some counter or adders in a partial product row while the tree topology arrangement of the compressors and their interconnection accumulate the partial product. A Gajski’s rule had been used to evaluate the performance of the multiplier and the result shows that the new multiplier has reduced delays in producing the output. The new multiplier architecture has reduced delays to almost 2% to 7% compared to other multipliers. The high speed multiplier was then extended to develop a Floating Point (FP) multiplier. The FP multiplier had been successfully designed using Altera Quartus II software and implemented on MAX EPM7182SLC84-7 device. The result showed that the FP multiplier is 38% faster compared to conventional FP multiplier. In term of size, the FP multiplier is 26% bigger than conventional circuit. However the increase in area of the circuit can be tolerated since the aim was to enhance the speed of the FP Multiplier.
      2  5
  • Publication
    Feature-based face recognition system using utilized artificial neural network
    ( 2009)
    Chai Tong Yuen
    This project aims to reduce the effect of critical conditions such as excessive illumination, facial expressions, hairstyles, beard and moustache which have affected the performance of face recognition since ages ago. The main contributions of this project are the automatic algorithms for mouth detection, facial features cropping and face classification. First, the algorithm will detect a human face and irises. Second, the mouth region is estimated by using geometric calculation based on the irises positions. A proposed algorithm which combines RGB color map and corner detection techniques will detect the mouth corners. Then, the proposed features cropping system will crop the detected iris and mouth automatically. These features are fed into the backpropagation neural network. The proposed architecture contains two neural networks. The second network merges the results from template matching and first neural network to reduce wrong recognition rate and improve the performance of neural network. The proposed automatic feature-based face recognition system has efficiency more than 95% under the stated critical conditions. All the experiment results are studied to prove the quality and uniqueness of this research.
  • Publication
    Web-based data acquistion system using a 32 bit single board computer and GNU/LINUX
    ( 2009)
    Wan Muhamad Azmi Mamat
    Most of the previous research in Data Acquisition System (DAS) had used Personal Computers (PCs) as hardware platform which were bulky and not portable. In this research, a Portable Embedded Sensing System (PESS) has been developed using commercial off-the-shelf (COTS) embedded system. Current COTS technology provides more flexibility in term of portability, scalability and configurability. PESS is made-up of an integration of TS-5500 Single Board Computer (SBC) as its computing core, a matrix keypad, a LCD display and sensors that attached to the interfacing circuit. As for the software part, PESS uses the open source GNU/Linux that allows modification to its libraries and device drivers. PESS has been extended by enabling a TCP/IP network connection to a server in order to accommodate bigger data archiving. These two-nodes network-based system is called PESS-n which divided to PESS and PESS-Server. PESS-n is equipped with an error-correction mechanism that can minimize data loses in the event of network failures, in addition to sending the backup data. A user interface has been developed at PESS-Server side to allow the acquired data to be presented in graphical format as well sharing of data via Internet. On the analog acquisition, not more than three steps resolution for the average bit of error has consistently been achieved. As for the network data transfer performance, both Transmission Control Protocol (TCP) and User Datagram Protocol (UDP) have been evaluated. While UDP provide faster recovery times during simulated network failures, it has limitation up to 64 KB of data payload only. As for the TCP, it has been able to transmit large data up to 1.6 MB which equal to fourteen days of data. It is found that the data losses of TCP and UDP are very small (2-3 unit of data).
  • Publication
    Biceps brachii surface EMG classification using neural networks
    ( 2009)
    Chong Yee Lin
    This thesis presents an approach of MATLAB-based system for clinical rehabilitation monitoring application. The main rationale for the development of such a system is that the pattern of the EMG signals elicited may differ depending on the activity of the muscle movement. Therefore, this research aims to study EMG signals elicited from biceps brachii muscle and classify the signal pattern to their respective class of activity. The proposed system consists of two main parts. The first part is about the development of an EMG acquisition platform. This platform consists of three modules; acquisition module, preprocessing module and feature extraction module. The acquisition module is used to acquire EMG signals from the subject. Several signal processing methods are carried out in the preprocessing module, where the EMG signal will undergo a series of processes like filtering, rectification and integration. After preprocessing, the signal is passed to the feature extraction module. In this module, statistical features such as mean, maximum, variance and standard deviation are computed to represent the signal pattern. The second part is regarding EMG pattern classification using neural networks. Feedforward BackPropagation Network (BPN) and Probabilistic Neural Network (PNN) are chosen as the classifiers to classify muscle activities. In the experimentation phase, 30 female subjects took part in this study. They were asked to perform several series of voluntary movement with respect to biceps brachii muscle. The experimental results show that EMG signals of different biceps activity is differed and simple statistical features are sufficient to represent the EMG pattern. The proposed BPN with Levenberg-Marquardt (LM) algorithm and PNN had achieved an overall classification rate of 88% while BPN with Resilient-Propagation (RP) algorithm achieved an overall classification of 87.11%. With these satisfactory results, the effectiveness of the proposed classifiers in EMG pattern classification problem is proven.
  • Publication
    Design, fabrication and characterization of CMOS ISFET for pH measurements
    ( 2009)
    Chin Seng Fatt
    The Ion Sensitive Field Effect Transistor (ISFET) is a potentiometric pH sensor that is easily adapted to a wide range of chemical, biochemical and biomedical applications. The operation of an ISFET is based on the surface adsorption of charges from the test solution in the solid-electrolyte interface that is part of the gate of the ISFET. As a result of this process, the threshold voltage of the ISFET is modulated.This thesis describes the design, simulation, fabrication and characterization of ISFET for pH measurement of an aqueous solution. Prior to fabrication, the ISFET is simulated via TCAD TSUPREM4 process and MEDICI device simulator. The ISFET is fabricated in-house in the Micro Fabrication Cleanroom Laboratory (MFCL) at Universiti of Malaysia Perlis (UniMAP) by using CMOS fabrication technology. This goal is achieved due to the compatibility of ISFET and CMOS. Silicon nitride was used as an ion sensitive membrane and it was deposited by using Plasma Enhanced Chemical Vapour Deposition (PECVD) technique. A total of six masks were used in this fabrication to create the CMOS ISFET. The ISFET fabricated is aimed at pH measurement of aqueous solution. In order to obtain an accurate characterization of the ISFET, a semiconductor characterization system (SCS) comprises of a micro probe station and a parameter analyzer was utilized. For the analysis of ISFET in test solution, an Ag/AgCl electrode is used as a reference electrode and three types of standard aqueous pH buffer solutions of pH 4, pH 7 and pH 10 were used during the experiment of ISFET analysis. The sensitivity of the ISFETs measured is 40mV/pH for n-channel ISFET and 30mV/pH for p-channel ISFET. These results demonstrate that the in-house fabricated CMOS ISFET is functional as expected.
      2  6
  • Publication
    Fabrication and characterization of silicon based vertical electrode nanogap biosensor for protein detection
    ( 2009)
    Norbi Hayati Mohd Noor
    The nanogap biosensor is a new class of device that has attracted attention and great interest among the researchers due to their potential applications in nanotechnology. This nanogap device which are fabricated using standard Complimentary Metal Oxide Semiconductor (CMOS) technology, have the potential to serve as the biomolecular junctions because their size reduces electrode polarization effects regardless of frequency. This junction technology is essentially a biology-to-digital converter system that enables real time conversion of biomolecular dielectric signals into digital information. This nanogap biosensor consists of a heavily doped silicon substrate electrode and poly-silicon electrode vertically separated by a fixed distance of 80 nm silicon oxide spacer. The process flow development in this research consists of detailed parameters and recipes to define the nanogap spacer. Two (2) types of masks are used in the process which are the Electrode Mask and the Aluminum Pad Mask. Both masks are designed by using the AutoCAD software and transferred onto a transparency. The main focus in this research is to create the gap spacer by using Inductive Coupled Plasma – Reactive Ion Etch (ICP- RIE) to etch the poly-silicon layer and buffered hydrofluoric acid (HF) to etch the silicon oxide layer. However, the silicon oxide was not completely etched, so that the remaining will act as the mechanical spacer gap. The final step involved sputtering and patterning aluminum onto contact pads using a standard photolithography technique. This was done to help minimize the variability in contact resistance when the nanogap device was probed. The overall goal of this research is to design, fabricate, characterize, and test the silicon based vertical electrode nanogap biosensor that will be used to detect and identify target proteins in aqueous solution.
      2  11
  • Publication
    Design and fabrication of quantum dot single electron transistors using scanning electron microscopy-based electron-beam nanolithogrphy
    ( 2009)
    Sutikno
    Quantum dot single-electron transistor (QD SET) is a nanoscale device operated at very low temperature. To fabricate QD SET operated at room temperature, QD must be fabricated in diameter of 10 nm. QD SET promises very small integrated circuits with ultralow-power consumption. In this research, a QD SET was designed using ELPHY Quantum GDSII Editor and fabricated using top down method. The QD SET masks design consists of SET mask for source-drain formation, SET mask for point contact and SET mask for metal pad. In addition, side gate and QD were designed in the same layer as source-drain. QD SET was designed using GDSII Editor with the following dimension: source-drain (3 μm x 3 μm), QD (10-30 nm in diameter), tunnel barriers (8.365 nm in width), side gate (3 μm x 3 μm) and metal pad (20 μm x 10 μm). Silicon on insulator (SOI) was used as the starting material and e- beam lithography system was used to transfer masks patterns. Negative resist ma-N 2403 was used to fabricate source-drain, QD, side gate and metal pad. Whereas positive resist 495K PMMA was used to fabricate point contact. To fabricate QD, silicon was etched using inductively coupled plasma (ICP) etcher and its parameters were optimized. The optimum etch time is 75 s and the optimum oxygen flow rate is 28 sccm. The smallest possible QD etched using ICP etcher in this research is 63 nm. To shrink QD dimension, silicon QD was oxidized through pattern dependent oxidation (PADOX) process using rapid thermal processing (RTP) and furnace. In this research, oxidation time using RTP was optimized in the range of 5-30 s at 1000 °C. Etched silicon samples were oxidized using furnace at 1000 °C in the oxidation time range of 5-30 min. The oxygen flow rate and the nitrogen flow rate were both set at 1 l/min. SiO2-embedded-silicon was characterized using transmission electron microscopy (TEM). The dimensions of QDs in the range of 10-30 nm were achieved and the oxidation rate was optimized as well. The nano multi layers alignment was done using SEM-based e-beam lithography and platinum was used as nano mark.
      2  14
  • Publication
    Fabrication and characterization of microfluidic field effect transistor on silicon substrate
    ( 2010)
    Maizatul Zolkapli
    The development of a silicon-based microfluidic field effect transistor has been carried out. The main objective of this study is to present from concept, the design of a microfluidic FET and to develop its appropriate process flow in fabricating the microfluidic FET on silicon wafer, which will finally be characterized using a suitable test methodology. Hence, fabrication on a p- <100> 4 inch silicon wafer by photolithography, wet chemical etching, thermal oxidation, diffusion and metallization with focus on a liquid conduction path has been executed. A three level photo mask has been designed via AutoCAD and chrome printed on soda-lime glass. The basic structure of the device is adapted from the conventional MOSFET structure and redesigned to incorporate a liquid channel in its operation. Therefore, the functionality remains unchanged but the principal conduction path is replaced by a fluid instead of a doped semiconductor. Two reservoirs are connected via a channel with source and drain regions doped on opposite sides of the liquid channel to reduce conduction through the substrate. They are placed as far away from each other in order to minimize electron flow through the fluidic channel when not filled with fluid. The channel widths are set to five sizes, which are 5 μm, 20 μm, 50 μm, 100 μm and 500 μm in order to study the effect of the transistor characteristics against channel size. The electron mobility in the channel is significantly affected due to the presence of polar liquid. The electron drift velocity now undergoes more collisions with mobile water molecules, which is itself polar and hence affected by the applied gate electric field. The channel profiles are inspected with the aid of stylus profilometer and SEM. The capping issue of the gate on the channel i.e. a void is addressed using a thin layer of single-side aluminum coated glass glued onto the silicon surface. This however results in higher threshold voltage as the silica thickness is about 80 μm, which is much thicker than the normal MOSFET oxide. Typically the thickness of the oxide layer in MOSFET is in the range of 0.02 - 0.1μm. Therefore, this causes higher reduction in electric field at the gate area. Testing of the devices commences during the fabrication process where the various resistivity, grown layer thicknesses and other parameters are measured. However, these measurements do not give an insight towards the final device performance. Thus, an electrical test is performed on both conditions, with and without liquid inside the channel using the semiconductor parametric analyzer, curve tracer and a high current circuit. I-V characteristics and resistivity of the devices is analysed and the results show that there is some current and voltage relation and the characteristics does conform to the theory. However, the device can not be categorized either as PMOS or NMOS since the channel is undoped. The resistance is reduced by one order for wet condition as compared to dry condition. This again shows that the presence of water molecules in the channel improves the carrier mobility.
      2  3
  • Publication
    Design of subsystems for multiband wireless transceiver
    ( 2010)
    Arjuna Marzuki
    This thesis deals with the development of subsystems for wireless application. The subsystems are Low Noise Amplifier (LNA), Medium Power Amplifier (MPA), Demodulator, Variable Signal Generator (VSG) and Voltage for Current Source (VCS). Several issues such as suitable multiband design flow, robust voltage source for current source, multiband local oscillator for I/Q mixer and high speed switch must be solved. A new design methodology of integrated circuits for multiband application is presented. The design methodology is modified from a typical Monolithic Microwave Integrated Circuit (MMIC) flow. Core based design, parasitic aware approach and power constrained optimization are introduced into the new design flow. Three subsystems circuits of a typical wireless transceiver are designed using the proposed new design flow and described in this thesis. The circuits are LNA, MPA and broadband amplifier. The same core circuit topology is used as main block to design 2.4 GHz and 3.5 GHz LNA and MPA. A power constrained optimization is applied to a test case amplifier i.e. broadband amplifier to get the optimized RF performance. The optimization is simulation-based technique. A 0.15 9m 85 GHz PHEMT is used in designing the LNA, MPA and broadband amplifier. The research on the demodulator is targeted for multiband application and low current consumption. The demodulator was designed for Wideband Code Division Multiple Access (W-CDMA) communication system. Tied collectors at the last two MSDFFs is employed to ease the multiband option. The design of demodulator contained 2 mixers, a local oscillator (LO) divider, negative resistance circuit, buffer amplifiers and bias/control circuits. The Voltage for Current Source is designed using Proportional to Absolute Temperature (PTAT) and Complementary to Absolute Temperature (CTAT) sources with combination of transistors and resistors. The VCS is used to provide voltage for current sources of RFIC blocks in the demodulator. A 0.35 µm SiGe BiCMOS technology with T f = 45 GHz, max f = 60 GHz and Noise Figure = 0.8 dB at 2 GHz was used for the design of demodulator and VCS. A variable signal generator that is capable of fast switching between different center frequencies is designed. The switching time is 4 ns and the three center frequencies at the lower band (UWB bands) are selected, which are 3.35 GHz, 3.85 GHz and 4.35 GHz. The structure of the variable signal generator is based on the topology of active oscillators. By using a switching network, the different frequencies from different cross-coupled LC oscillators are switched within 4 ns. In this design, a new topology of NMOS switch based on series-shunt configuration is proposed so that it is able to pass the signal from oscillators to output without transition spike and free of charge injection problem. A 0.18 µm CMOS technology is used to design the VSG. The MPA core circuit measurement result has at least 0.5 dB differences in power gain compared to parasitic aware simulation result. A broadband amplifier of 12.5 GHz 3-dB bandwidth is designed using power constrained optimization technique. The Figure of merit (FOM) of broadband amplifier is 0.4 better when power constrained optimization is applied to the design process. Thus, this new design flow or methodology would provide considerable improvement in reducing design cycle and in increasing the chances of first time right integrated circuit. A fabricated Demodulator prototype was measured and was found to agree with the simulation results. The prototype worked in the region of 190 MHz input frequency and 0-35 MHz output frequency. The prototype had also met the specifications for the W-CDMA hand phone receiver. It achieves EVM of 2.9 %. It also achieved gain ripple of 0.12 dB, gain mismatch of 0.1 dB and phase mismatch of O 25 . 1 . Simulated VCS could provide 2 % current variation across temperature for a current source. Finally, the design consisting of mixers, frequency dividers, buffer amplifiers and bias/control circuits consumes 4 mA with 3 V power supply. The performance of the variable signal generator is verified using Cadence simulation at a supply voltage of 1.8 V. The simulation results indicate that the variable signal generator is able to produce a signal with three center frequencies, i.e. 3.35 GHz, 3.85 GHz and 4.35 GHz at 400 mV peak-to-peak within every 4 ns. The hop between the frequencies is less than 1 ns.
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  • Publication
    Design and development of low cost biceps tendonitis physiotherapy monitoring system using surface EMG electrodes for automated rehabilitation
    ( 2011)
    Poo Tarn Shi
    Electromyogram signal (EMG) is an electrical potential signal generated from EMG electrodes attached on the skin when there is a contraction of muscles. These signals are useful in kinesiology study, biomedical research, clinical usage, physiotherapy and muscle dysfunction diagnosis. However, current acquisition systems that are available in the market are expensive and bulky. Therefore, this research attempts to design and develop a low cost EMG acquisition system for monitoring biceps tendonitis physiotherapy. The proposed EMG acquisition system uses surface EMG electrodes for EMG signal detection. In the design of the EMG acquisition circuit, the EMG signal is amplified in two stages to convert it into an observable scale. The inherent noise acquired from the power line of 50Hz frequency is eliminated with a single hybrid IC notch filter. Then, the rectification and low pass filter modules will convert the EMG signal to a linear envelop waveform. This signal is then sampled by a signal processing module. The analogue linear envelop EMG signal is sampled into a 24 bit digital data. An algorithm is developed and coded to send the digital data into the computer. The digital EMG data is then reassembled and displayed using a software scope on the computer. In order to test the system, 20 subjects are requested to perform a set of rehabilitation exercise and the EMG signals were recorded. The results collected from this proposed EMG acquisition system is compared with the readings obtain from a commercial product. This comparison gives an average error of ±0.05m V in the readings. Hence, the proposed designed is deemed to be satisfactory.
  • Publication
    Development of a circular complementary split ring resonator microstrip antenna for high altitude platform station
    ( 2011)
    Mohd Ezanuddin Abdul Aziz
    In this thesis, the influences of Circular Complementary Split Ring Resonators (CCSRR) and air gap within the circular microstrip patch antenna structure are investigated for the use of Malaysia’s future High Altitude Platform Station(HAPS) wireless communication. The proposed antenna is designed to operate from 5.850 GHz to 7.075 GHz spectrum band using microwave laminate RT/D 5880 (εr = 2.2 and thickness of 1.82 mm). The antenna structure was organized into three separate layers consisting of circular copper sheet as the ground plane (layer number one), an undersized main radiator, where the electromagnetic signal and energy gathered and stored, focuses and passes through (layer number two) to resonate its above layer and the etched slotted split ring resonators on the dielectric laminate (layer number three) supported by low dielectric foams (εr = 1.2). All layers are separated by an air gap, simulated and optimized using the Computer Simulation Technology Suite (CST), Microwave Studio software. The distance of air gap, the positioning of coaxial feed together with a small circular copper patch, the number and the width of the split ring resonators corresponding to each individual circular patch are varied and analyzed as the key player studies. The results of the return losses, VSWR, realized gain and farfield characteristics either in 2D, 3D or polar plot views obtained are compared and analyzed. Measurement of the fabricated antenna showed deep line return loss below -10 dB beginning at 5.75 GHz to 7.25 GHz as compared to simulations which were 5.0 GHz to 7.5 GHz (VSWR 2:1). Overall, the antenna, once compared between its simulations and fabricated managed to produce a stable 5 dBi gain and directivity along the targeted spectrum band. The results show that inclusion of split ring resonators have enhanced and improved the antenna fundamental performance and in terms of sustaining the targeted bandwidth. The CCSRR structure also managed to produce real part of permittivity and permeability readings into negative values through a two port numerical simulation, part of a metamaterial simulation experiment, that is to investigate Double Negative (DNG) characteristics. DNG characteristics helps to improve surface current flow raised the gain and beam phase within the frequency spectrum (the more negative the values of ε and become, a slight increase to the gain can be observed). CST MW powerful transient solver was able to simulate the antenna integration with a miniaturized plane the stratospheric M55. Deploying two antenna units on the M55 aircraft wings (separated at 23 meter apart, the total wingspan = 37.46 meter) have created an array formation and further increased the signal gain. The antenna produced maximum E-plane and H-plane co and cross polarization difference in the magnitude of 3.5 dB and E-plane half power beam width (HPBW) of 200.