Theses & Dissertations

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https://hdl.handle.net/20.500.14170/209

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Now showing 1 - 5 of 363
  • Publication
    FPGA prototyping flow optimization by using failed path fixes and manual clock distribution techniques
    (Universiti Malaysia Perlis (UniMAP), 2019)
    Salahuddin Savugathali
    The purpose of this research is to review and propose a new flow in FPGA Prototyping Flow using a Synopsys Protocompiler tool to solve the stated problem. A fascinating property of a latch-based design is that the combinational path delay is allowed to be longer than the clock cycle as it can borrow time from the shorter paths in the subsequent logic states. Time Borrowing technique is a common approach used to satisfy timing violation in an FPGA prototyped design. However, based on previous studies, more efforts are required to produce an efficient result in closing the timing violation, where lead us to propose a Failed Path Fixes technique. This approach is meant to fix the failed path in a latch due to the gated clock conversion (GCC) process during the synthesis stage which could lead to the timing violation. A solution for prototyping a multi-million logic gates of ASIC/SoC circuit into the FPGA platform for verification purpose is by partition the design into multi-FPGA. This research is focusing on the required partition requirement to successfully prototype the large SoC circuit into the multi-FPGA. The presence of cut clocks in a circuit after partition stage will result in the failure in routing stage due to the congestion error. Therefore, an approach proposed in this research to resolve this challenge is Manual Clock Distribution technique, so that design is able to meet the partition requirement to complete the prototyping process into multi-FPGA. The combination of our Failed Path Fixes and time borrowing technique are able to solve the timing violation problem by eliminating the unnecessary path created by protocompiler tool. Comparison of numbers of negative slack before and after our proposed technique is applied resulting 90% improvement. The manual clock distribution technique proposed has been able to solve the cut clock issue that leads to routing congestion problem when partitioning a circuit into two FPGA chips. With our proposed technique, all partition requirements are met and I 00% cut clock elimination is achieved.
  • Publication
    Enhancement of host-based and network-based mobility management protocols in wireless mesh network
    (Universiti Malaysia Perlis (UniMAP), 2018)
    Hoh Wei Siang
    Since the dependency of human toward the Internet, this has rapidly raise the usage of internet which may cause congestion and intermittent connection issues. The Wireless Mesh Network (WMN) was introduced to overcome the intermittent connection issues and caters rural area in order to effectively increase the scalability of network with lower construction cost. However, in WMN, there is no specific mobility management protocol that is appointed to handle the location management and handoff management of Mobile Node (MN). Besides that, the MN also faces the difficulties in choosing the suitable mobility management protocols to perform the handover process either in inter or intra domains since the current mobility management protocol handles both intra and inter domains mobility management. Single mobility management protocol needs to handle beacon update and acknowledgement for inter and intra mobility managements. This causes significant delay and distortion which decrease the efficiency of wireless communication. Having known this issue, the aims of this thesis are: firstly, performance evaluation and comparison of various mobility management protocols in WMN environment. The Host-Based and Network-Based mobility management protocols are consolidated in WMN environment and separately implemented and handles the inter and intra mobilities. MIPv6 and FMIPv6 are chosen to operate in intra network scenario while for inter network scenario, HMIPv6, FHMIPv6 and PMIPv6 are appointed to handle the operation. The perfonnance results show that the FMIPv6 have better perform than MIPv6 in intra network scenario. While for inter network scenario, the PMIPv6 is outperformed which compares to HMIPv6 and FHMIPv6. Secondly, the target is to enhance the performance of standard FMIPv6 in intra network scenario. The Optimise FMIPv6 (O-FMIPv6) was introduced with new fast handover scheme based on the standard FMIPv6 to operate in intra network scenario. For enhanced fast handover mechanism, when the MN senses lower signal strength, MN advertises to the neighbour network for the need to attach to the new higher signal strength access point. MN informs the new access point of the need to change to the new access point before the process of handover. Thus, this can reduce the handover latency of handover processes. Thirdly, it is to propose route optimise PMIPv6 (RO-PMIPv6) with new route optimisation scheme which modifies theLMA and MAG entitles. When there is a need to connect to different hierarchical access points, only LMA involves to inform the different hierarchical access points and CN before and after the handover process is performed. This can reduce the time of handover process and thus decreases the handover latency and increases the wireless communication efficiency. For both intra and inter domains mobility management over WMN, the end-to-end delay, packet delivery ratio (PDR) and throughput are measured to show the optimisation of the proposed O-FMIPv6 and RO-PMIPv6. Lastly, the results show that the designed intra domain mobility with O-FMIPv6 and the inter domain mobility with RO-PMIPv6 enhanced the mobility management performances. The O-FM1Pv6 performs 2.2% lower in end-to-end delay, 3.7% higher in PDR and 5.4% higher in throughput as compared with standard FMIPv6. The RO-PMIPv6 performs 58.3% lower in end-to-end delay, 2% higher in PDR and 2. 7% higher in throughput as compared with standard PMIPv6. With this enhanced mobility management, it is believed that with the implementation of the designed mobility management protocols, this can reduce latency, increase throughput and decrease distortion. With these criteria, the future aims of wireless communication while moving is made possible which eases the communication between human.
  • Publication
    DSP implementation of embedded coding for wavelet based image compression on the TMS320C6713
    (Universiti Malaysia Perlis (UniMAP), 2015)
    Iskandar Zulkarnain Shamsudin
    As the new standard compression method for the JPEG 2000, the discrete wavelet transform (DWT) is quickly finding more and more uses in the image compression department. With the numerous and repetitive calculations needed to fmd the coefficients of a large image, speed is critical when implementing a wavelet filter bank to represent the DWT in hardware. The objective o f this thesis is to implement a Embedded Coding for Wavelet Based Image Compression on the TMS320C6713. The reason of this because of the time execution for the embedded coding on computer is take more time to compress one image. TMS320C6713 is a embedded board that provide more fast time execution so that the embedded code can process more fast than the computer.
  • Publication
    Simulation of graphene band structure and fabrication of graphene field effect transistor
    (Universiti Malaysia Perlis (UniMAP), 2018)
    Siti Fazlina Fauzi
    This thesis presents an approach in exploring graphene for digital electronics, as well as analogues. For digital electronic application, this work focused on opening and tuning the monolayer graphene band gap based on the inclusion of dopant atoms, by using AtomixKit Simulator from Quantum Wise. Two sets of simulation have been carried out, that are, to study the graphene band structures based on the effect of asymmetrical bilayer graphene layers and doping the monolayer graphene with boron and Oxygen atoms. Results have shown that monolayer and symmetrical bilayer graphene exhibit zero band gaps, while asymmetrical bilayer graphene provides a band gap of 0.35 eV. The opening of energy band gap in asymmetrical hi- and multi-layer graphene is limited and reduces electron mobility. So another approach to open the band gap without disrupting the high electron mobility in monolayer graphene, is by doping the graphene. This work has shown that the inclusion of dopant atoms in monolayer graphene results in an increase in the band gap, with increased number of dopant atoms. The position of the dopant atoms in monolayer graphene also significantly affects the band gap opening. It is obtained that Oxygen atoms in graphene give rise to higher band gap openings compared to boron atoms. This ability to modify the monolayer graphene band gap can be applied for many digital electronic applications. For analogue application, this research focused on investigating the effect of channel length and gate oxide thickness of graphene field effect transistor (GFET). This GFET fabrication required a good coverage of monolayer graphene. This work has performed an optimization in the graphene transfer process, in which a stamping method using a wooden block is suggested. A proper cleaning process in acetone is also crucial in order to obtain a good layer of graphene before GFET can be fabricated. In this work, the GFET performance is investigated based on the charge carrier mobility taken from both transportation of electrons and holes. The GFETs have been fabricated with two different gate oxides with thicknesses of 63 nm and 83 nm with channel lengths varied from 250 𝛍m to 650 𝛍m. Results have shown that the electron mobility in GFET increases as the channel lengths decreases. The same pattern is observed for hole carrier mobility. However, it is obtained that the electrons and holes mobility decreases as the gate oxide thickness increases. It can be concluded that the GFET channel length and gate oxide thickness play an important role in determining the GFET performance, as the speed of the device increases with shorter channel and thicker gate oxide.
  • Publication
    Synthesis and electrical characterization of Nd-Doped BaTiO₃ for anti-resonance piezoelectric device
    (Universiti Malaysia Perlis (UniMAP), 2017)
    Tuan Amirah Tuan Sulong
    Severe implications by lead usage in microelectronic industry to the environment forced the findings of lead-free ceramics alternatives in recent years. Barium Titanate (BaTi0₃) based ceramics are particularly interesting among the various lead-free ceramics due to its high permittivity, low dielectric loss and exhibit piezoelectric effect. In this study, Neodymium (Nd)-doped BaTiOJ with composition ofBa1-xNdxTi03 at range (0 ~ x ~ 0.13) were prepared via conventional solid state method at high temperature. X-ray diffraction analysis shows that for Nd-doped BaTiOJ, the phase purity was obtained at final heating temperature of 1400 oc for 12 hours. Single phase ofNd-doped Ba TiDJ was observed from 0 ~ x ~ 0.1 0, however, the tetragonal distortion in undoped BaTi0₃ decreased with increasing x. The samples remain tetragonal until x ~ 0.015 and were cubic for 0 . 03 ~ x ~ 0.1 and appear to coalesce at x = 0.13. Maximum permittivity shifted to lower Curie temperature (Tc) from 120 octo 90 oc by doping at tetragonal region and remain linear without maximum at cubic region. For electrical properties, the sample ofx=0.005 exhibit a very high permittivity at room temperature which is 2586, lowest dielectric loss of 0.03, high piezoelectric charge constant about 55 pC.N-1 and high piezoelectric voltage constant about 0. 7 V m.N-1. The novelties in this study was the piezoelectric study was determined at doping concentration of 0 ~ x ~0 . 015 , whereby the piezoelectric properties increased with increasing poling voltage.
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