Theses & Dissertations
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PublicationSuper-resolution image reconstruction using interpolation-based method for biometric images( 2024)Super-resolution is a widely applied technique in enhancing image resolution. It has uses in medical imaging, satellite imaging and especially in biometric identifications. Three main methods in super-resolution are learning-based, reconstruction-based, and interpolation-based methods. The learning-based methods often requires big, external data and the resultant image output relies heavily on the features of the training image data while reconstruction-based methods were based on the presumption of the low-resolution image is a degraded version of a high-resolution image and the computational complexity that were required to reverse the degradation were often high and the resulting output image quality were inconsistent. This research proposed a Gabor-weighted interpolation method to super resolve a low-resolution image into a high-resolution image since the common problem in an interpolation-based method was its tendency to create edge artifacts, jaggedness or over-smoothing. The Gabor-weighted interpolation was done only at the edge areas of an image and utilised the Lanczos interpolation to interpolate the non-edge areas. The proposed method was analysed quantitatively and qualitatively and also included multiple edge-based analysis. The proposed method was compared to other super-resolution methods including learning-based, reconstruction-based, interpolation-based, and hybrid methods. The results showed that the proposed method provide a good Image Quality Assessment (IQA) results consistently across the tested images and the application of the proposed method on biometric images provide good results with a high Fingerprint Matching score compared to other methods which is 1703.475. The proposed method yielded an average of 33.698 Peak Signal-to-Noise Ratio (PSNR) value and 16.177 Edge-Based Image Quality Assessment (EBIQA) value for the general images and an average of 35.621 PSNR value and 18.608 EBIQA value for biometric images. The proposed method also yielded clear and pleasing effects on the high-resolution images based on the naked eye comparison presented.
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PublicationDesign of high-efficiency CMOS Class E power amplifier with active inductor for 5G applications( 2024)5G technology has made huge advancements in the past few years, especially in the speeds and applications. They have much faster speeds compared to 4G technology. These applications require components in their transceiver system, which can transmit and receive information through a network. One of those components is the power amplifier (PA), a device that can amplify the signal. However, the efficiency of power amplifiers is limited at high frequencies. The reduction in the efficiency of the device mainly happens because of the low Q-factor of the components that make up the design of the circuit. The worst contributing factors are the on-chip inductors, which can occupy a significant amount of area and have the greatest impact on the device due to their low Q-factor. The low Q-factor affects efficiency due to the high losses from the on-chip spiral inductors. The objective of this research is to design high power added efficiency (PAE) of PA to enhance the performance of the overall transceiver. Therefore, a high-quality active inductor (AI) is proposed to replace the spiral inductor in PA circuit to reduce losses and thus increase the efficiency of PA. The proposed active inductor employed a fully differential structure with a cascode current mirror. The AI is designed and simulated in Cadence Virtuoso using Silterra CMOS 0.18 μm technology. Further, the proposed AI is integrated with a class E PA. Class E PA consists of two stages, which are a driver stage and a class E power stage. The post layout simulation shows that the active inductor achieves a high-quality factor of 16,000 at 3.0 GHz frequency, however the Q factor is reduced to 500 at the targeted frequency of 3.5 GHz. The Q factor at targeted frequency at 3.5 GHz is still reasonable to reduce the losses. Furthermore, the active inductor is added to the output matching network of PA to replace the on-chip spiral inductor. The pre-layout simulation results indicate that the PAE is increased from 67.33 % to 75.75 % when spiral inductor is replaced by AI. Similarly, the PAE increased to 63.88 % from 50.6 % in a post-layout simulation. The discrepancy between pre and post layout is due to the parasitic effects.
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PublicationA wearable microfluidic device integrated with a sensor and potentiostat for sweat sodium monitoring( 2024)Wearable sensing devices, including the application of human sweat monitoring, are currently gaining attention for noninvasive purposes such as fitness tracking and even disease diagnostics. However, these devices encounter challenges related to reliability and data accuracy. For instance, the challenges include the collection of limited sample volumes, the efficiency and continuous flow of the sweat sample collector, sensor reliability, and the accuracy and stability of the electrochemical device. A microfluidic device with micro-sized channels has been developed to improve sample volume for collecting limited sweat samples in the microliter range and to reduce contamination. It has also been optimized for effective sweat flow by utilizing a water-washable material, which provides the microfluidic device with a hydrophilic surface. The microfluidic device has been designed with a vertical channel that enhances gravitational force to facilitate continuous fluid flow, prevent backflow, and reduce the mixing of old and new sweat concentrations. The developed potentiostat, an electrochemical analyzer, has been designed with a compact and lightweight form factor suitable for wearable applications. This device accurately measures electrical current across a range from milli- to nanoamperes when the voltage is varied. Dummy cell tests showed that the electrical properties are stable, with both the commercial and developed potentiostats exhibiting similar curve shapes. In sodium measurement tests, the device demonstrates high-performance accuracy, supported by a 95% confidence interval from Bland-Altman analysis. Device variability is characterized by a coefficient of variation of less than 4% and an intraclass correlation of 0.998 in the 10 mM to 200 mM sodium ion range. The device also shows good selectivity for sodium ions in the presence of other interfering ions, as it shows a small mean difference for each different concentration. It exhibits good stability, with a small standard deviation of 7. The results from the exercise activity reveal a decrease in sodium levels from 112 nA to 91 nA within 10 to 30 minutes, corresponding to concentrations ranging from 101 to 67 mM. This decrease aligns with the expected loss of sodium in the human body over time. In conclusion, the proposed wearable devices offer continuous flow capabilities and accurate sweat sodium measurements, addressing key challenges in current wearable technologies.
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PublicationCCEP: an efficacious content caching and eviction priorities for high performance of in-network caching in information centric networking( 2020)Nowadays, Internet usage is shifting towards information distribution and retrieval, with data access becoming the norm. As a result, information-centric networking (ICN) infrastructure has emerged for the future Internet. ICN includes an in-network caching feature that allows contents to be cached in the network to provide efficient data delivery, thus increasing interest in providing the best caching strategy to manage contents over the ICN network. The default caching strategy adopted by ICN is Leave Copy Everywhere (LCE), where the content of the network is cached at all content routers along the downloading path. Thus, some problems appear such as the increase in caching redundancy and the low hit ratio of the cache, besides many cache operations (placement and replacement operations), which cause an increase in energy consumption. Since then, in-network caching has been one of the hot topics of ICN research to play a significant role in improving the network. Various caching strategies have been proposed to solve the drawbacks of LCE and enhance the performance of in-network caching in ICN. Nevertheless, these proposed caching strategies also still suffer from some disadvantages that render them inefficient for performance improvement. Therefore, this thesis proposes a new caching strategy named “An Efficacious Content Caching and Eviction Priorities for High Performance of In-Network Caching” (CCEP). It combines the advantages and overcomes the drawbacks of the existing caching strategies to provide distinguished performance in terms of hop reduction ratio, cache hit ratio, and cache operations. The CCEP strategy is based on caching priority and eviction priority for the content. Synchronously, the caching strategy calculates caching priority for content in each content router across the path between the user and the content source (server). Then, the content router with maximum caching priority will cache the content. When the cache is full and new content arrives to cache at the content router (content replacement), the caching strategy calculates eviction priority for all cached contents, and the content with maximum eviction priority will be evicted to cache the new content. The performance of CCEP was evaluated through simulations, and the results show that the proposed caching strategy achieves significant performance gains compared to the existing caching strategies. In more detail, CCEP was compared to the default caching strategy; CCEP can reduce the number of cache operations to 99.99%, and increase hop reduction to 1667.44%, and cache hit ratio to 1815.63%. It was compared to the best-caching strategy (MAGIC), and CCEP can reduce the number of cache operations to 21.65%, and increase hop reduction to 53.26%, and cache hit ratio to 17.43%.
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PublicationHigh performance 32-bit logarithmic number system for non-linear arithmetic operations( 2021)In a computer arithmetic, a straightforward algebraic property of a logarithmic number system (LNS) towards the multiplication and division are of importance. An improvised version of a LNS is needed since the non-linear computations at the addition and subtraction represent significant challenges. In addition, the complex function of the subtraction caused by singularity requires an enormous size of memory. This thesis focuses on the improvisation of two algorithms, namely the co-transformation and interpolation for a high performance 32-bit arithmetic unit. For the co-transformation procedure, the singularity region covered by the previous architecture is optimized to reduce the latency. Meanwhile, assorted interpolation schemes in addition and subtraction operations are also evaluated for a compact lookup table (LUT) to give a rapid and an accurate computation. The evaluation in this research work reveals an optimized LNS architecture with a double co-transformation technique which has an averagely 47% faster speed when it is benchmarked against the recent LNS design. From the proposed hybrid interpolation scheme, the speed and area of the new LNS design are found to be far more superior than the existing LNS design and are also on par with the recent floating-point (FLP) design. The amount of memory which is dominated by the co-transformation architecture can also be reduced. The proposed system is synthesized by selecting a Ladner Fisher (LF) adder as well as a Booth with Wallace Tree multiplier to boost the computation speed. It is found that the proposed system is able to provide an economical area with rapid computation while sustaining the accuracy better than the floating-point (BTFP), which is in agreement with the benchmarking results made against the previous logarithm number and floating-point units.