Noraini Othman
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Preferred name
Noraini Othman
Official Name
Noraini, Othman
Alternative Name
Othman, Noraini Binti
Othman, Norreha
Othman, Noraini Bt
Othman, Noraini (UUM)
Othman, Noraini A.
Othman, N. A.
Othman, N.
Othman, Noraini
Main Affiliation
Scopus Author ID
57189034221
Researcher ID
IAI-5023-2023

Research Output
Now showing 1 - 3 of 3
  • Publication
    Numerical simulations of innovative ground plane and double-gate configurations in thin-body and -buried oxide of SOI MOSFETS
    ( 2017)
    Noraini Othman
    The downscaling of transistors enables an increased in transistor density, faster switching speeds and greater complexity with no increase in power consumption. However, the scaling of the conventional planar MOS transistors appears to be reaching the end of the technology roadmap due to worsening performance variability and shortchannel effects (SCEs). One of the contenders anticipated to replace the current transistor architecture is planar ultra-thin body and BOX (UTBB) SOI MOSFET. The advantage of the thin-body SOI structure lies in its simple planar process which is fully compatible with the bulk silicon CMOS flow. In this research work, a particular attention is being given to the performance of UTBB SOI MOSFETs with its thin BOX in improving electrostatics behaviour namely of drain-induced barrier lowering (DIBL) of the thin-body as compared to thick BOX (UTB) SOI transistors for extending CMOS scalability. Subsequently, UTBB with different ground plane (GP) architectures and gate configurations (i.e. single-gate (SG) vs double-gate (DG)) are extensively studied through numerical simulations as possible candidates for the continuation of Moore‟s Law. In-depth study of the digital and analog/RF figure-of-merit (FoM) are carried out in a wide range of frequency (from 0.01 Hz to 100 GHz) in correlation with device operation mechanisms. It is discovered that an innovative GP formation made of localized GP of p-type in the substrate underneath the channel (referred herein throughout the thesis as GP-B) effectively suppress substrate depletion effects and shows better immunity against SCEs from the digital analysis viewpoint. Further improvements in the immunity against SCEs can be achieved in DG configurations where the impact of different GP architectures is amplified as compared to SG. Even though the use of DG configurations provides superior digital performance, lower current gain cut-off frequency (ft) values are produced than SG in the analog domain due to an increase of gate-to-gate capacitances (Cgg). Therefore, careful selections and trade-offs are needed when selecting a particular device structure where the results obtained in this research work contribute to the identifications of GP architectures and gate configurations (SG or DG) that can be adopted in device design to suit specific applications of either digital or RF.
  • Publication
    A controlled growth of carbon nanofibers (CNFs) on graphene
    ( 2023-12)
    Mishtha Fiyatillah
    ;
    Syarifah Norfaezah Sabki
    ;
    Norzilah Abdul Halif
    ;
    L K Wisnu Kita
    ;
    Muhammad Asri Idris
    ;
    Noraini Othman
    ;
    A F Abd Rahim
    Carbon nanofibers (CNFs) have superior properties such as high conductivity, good mechanical strength, high specific surface area, and chemical stability. CNFs-graphene hybrid material can be used as a high-quality electrode in electronics applications. In the CNFs on graphene synthesis, the growth parameters must be well controlled. This work observes the evolution of the CNF's growth on graphene on Ni at reaction temperatures of 800oC and 860oC and at different reaction times of 30 min, 60 min, and 120 min. This research aims to find suitable conditions for obtaining controllable growth of CNFs on graphene. Based on the SEM measurement, it was found that the 860oC reaction temperature at 60 min and 120 min reaction time led to longer and smaller widths of CNFs with high coverage and distribution on graphene. The CNFs on graphene formation were confirmed by the XRD analysis.
  • Publication
    Impact of nanowire radius and channel thickness with high-k gate dielectric in GAA-JLT
    ( 2023-12)
    Nilaventhiran Vespanathan
    ;
    Noraini Othman
    ;
    Syarifah Norfaezah Sabki
    ;
    Alhan Farhanah Abd Rahim
    As the transistor’s size becomes smaller, degradation in the short-channel effects (SCEs) becomes more apparent. This leads to research work on multi-gate transistors such as the Fin-Field Effect Transistor (FinFET) and Gate-All-Around (GAA) transistor, where the 3D architecture have been shown to have superior performance as compared to conventional planar transistor. Transistor without junctions (JLT) which realizes a single type of doping has also been gaining popularity for biosensor applications due to its superior electrostatic performances in terms of Drain-Induced Barrier Lowering (DIBL), off-state leakage current (Ioff) and Subthreshold Slope (SS). In this work, the impact of changes in parameters such as the gate oxide material, nanowire radius and channel thickness toward the performance of a Gate-all-around JLT (GAA-JLT) have been studied using TCAD simulator. It was found that smaller nanowire radius and thicker channel produces lower DIBL, Ioff and SS, with the use of HfO2 as gate oxide materials shows better results than Si3N4. Meanwhile, the impact of parameters variations seemed to be negligible on the on-state current (Ion). The outcome of this work can be used as a basis to understand the impact of structural parameters variations towards the performance of a more complex GAA-JLT structure.