In this work, we investigate the impact of employing silicon-on-nothing (SON) versus silicon-on-insulator (SOI) on the electrostatic performance of a transistor with various ground-plane (GP) structures of Lg = 10 nm through the use of Sentaurus TCAD simulator. The digital figure-of-merit (FoM) of interest includes the results of drain-induced barrier lowering (DIBL) which is a major indicator of a control of short-channel effects (SCEs). It is found that SOI devices produce a lower off-current (Ioff) as compared to SON. In terms of the different GP architectures, the introductions of various GP architectures were found to affect the values of DIBL in SOI whereas the impact on SON is negligible. It can be concluded that GP-B architectures with ground plane underneath the channel areas of SOI is most effective in suppressing substrate depletion effects as evidenced from the lowest DIBL produces.
