Noraini Othman
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Preferred name
Noraini Othman
Official Name
Noraini, Othman
Alternative Name
Othman, Noraini Binti
Othman, Norreha
Othman, Noraini Bt
Othman, Noraini (UUM)
Othman, Noraini A.
Othman, N. A.
Othman, N.
Othman, Noraini
Main Affiliation
Scopus Author ID
57189034221
Researcher ID
IAI-5023-2023

Research Output

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A Controlled Growth of Carbon Nanofibers (CNFs) on Graphene

2023-12-01 , Fiyatillah M. , Syarifah Norfaezah Sabki , Norzilah Abdul Halif , Kita L.K.W. , Muhammad Asri Idris , Noraini Othman , Abd Rahim A.F.

Carbon nanofibers (CNFs) have superior properties such as high conductivity, good mechanical strength, high specific surface area, and chemical stability. CNFs-graphene hybrid material can be used as a high-quality electrode in electronics applications. In the CNFs on graphene synthesis, the growth parameters must be well controlled. This work observes the evolution of the CNF's growth on graphene on Ni at reaction temperatures of 800oC and 860oC and at different reaction times of 30 min, 60 min, and 120 min. This research aims to find suitable conditions for obtaining controllable growth of CNFs on graphene. Based on the SEM measurement, it was found that the 860oC reaction temperature at 60 min and 120 min reaction time led to longer and smaller widths of CNFs with high coverage and distribution on graphene. The CNFs on graphene formation were confirmed by the XRD analysis.

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A study on the impact of silicon-on-nothing (SON) versus silicon-on-insulator (SOI) on the electrostatic performance of a transistor

2018-12 , Noraini Othman , Syarifah Norfaezah Sabki , Hasnizah Aris

In this work, we investigate the impact of employing silicon-on-nothing (SON) versus silicon-on-insulator (SOI) on the electrostatic performance of a transistor with various ground-plane (GP) structures of Lg = 10 nm through the use of Sentaurus TCAD simulator. The digital figure-of-merit (FoM) of interest includes the results of drain-induced barrier lowering (DIBL) which is a major indicator of a control of short-channel effects (SCEs). It is found that SOI devices produce a lower off-current (Ioff) as compared to SON. In terms of the different GP architectures, the introductions of various GP architectures were found to affect the values of DIBL in SOI whereas the impact on SON is negligible. It can be concluded that GP-B architectures with ground plane underneath the channel areas of SOI is most effective in suppressing substrate depletion effects as evidenced from the lowest DIBL produces.

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Impact of different doping concentrations on the digital and analog FoM of a junctionless transistor

2020-01-08 , Noraini Othman , Ring, Tan Shin , Syarifah Norfaezah Sabki

The miniaturization of transistors causes many challenges in producing high quality junctions for a conventional transistor. As conventional transistors getting smaller in size, there are several critical challenges such as low on-state current, Ion and high gate leakage current, Ioff. Junctionless transistor (JLT) is an alternative to conventional transistor with junctions as it is uniformly doped and has no doping concentration gradients. This work embarks to study the impact of various doping concentrations towards the digital and analog figure-of-merit (FoM) of a JLT. Simulations of a junctionless transistor were carried out by using Silvaco ATLAS TCAD Tools for gate length of 25 nm. It is found that the best doping concentration is of 1 × 1018 cm-3 as it produces the highest Ion while maintaining low Ioff of 1.31 × 10-06 A and 6.94 × 10-11 A respectively in the digital realm. In terms of analog FoM, the best doping concentration is also found to be of 1 × 1018 cm-3 as it produces the highest cut-off frequency, ft of 227 GHz.

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Impact of nanowire radius and channel thickness with high-k gate dielectric in GAA-JLT

2023-12 , Nilaventhiran Vespanathan , Noraini Othman , Syarifah Norfaezah Sabki , Alhan Farhanah Abd Rahim

As the transistor’s size becomes smaller, degradation in the short-channel effects (SCEs) becomes more apparent. This leads to research work on multi-gate transistors such as the Fin-Field Effect Transistor (FinFET) and Gate-All-Around (GAA) transistor, where the 3D architecture have been shown to have superior performance as compared to conventional planar transistor. Transistor without junctions (JLT) which realizes a single type of doping has also been gaining popularity for biosensor applications due to its superior electrostatic performances in terms of Drain-Induced Barrier Lowering (DIBL), off-state leakage current (Ioff) and Subthreshold Slope (SS). In this work, the impact of changes in parameters such as the gate oxide material, nanowire radius and channel thickness toward the performance of a Gate-all-around JLT (GAA-JLT) have been studied using TCAD simulator. It was found that smaller nanowire radius and thicker channel produces lower DIBL, Ioff and SS, with the use of HfO2 as gate oxide materials shows better results than Si3N4. Meanwhile, the impact of parameters variations seemed to be negligible on the on-state current (Ion). The outcome of this work can be used as a basis to understand the impact of structural parameters variations towards the performance of a more complex GAA-JLT structure.

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The impact of strained layer superlattice (SLS) to the emission and internal quantum efficiency (IQE) of a GaN LED

2020-01-08 , Min Tain Shi , Syarifah Norfaezah Sabki , Noraini Othman

Gallium nitride (GaN) light emitting diode (LED) has been used as highly efficient solid-state light sources to radiate a wide range of wavelengths in the visible spectrum. Larger currents drive bright LEDs, causes reduced efficiency which known as LED droop. Insertion of strained-layer superlattice (SLS) in GaN LED gives uniform electron distribution, lead to high emission and efficiency. The primary aim of this work is to investigate the operation of LED with the inclusion of SLS by simulation. The GaN LED was designed in cylindrically symmetrical configuration with the insertion of the InGaN/GaN SLS of 3 nm thick. This work investigates the effect of different number of SLS layers, which is represented by 1, 2 and 3 periods of SLS, which represent the total SLS thicknesses of 3 nm, 6 nm and 9 nm respectively. A GaN cylindrical chip of 700 nm diameters was designed with p- and n-type doped active region. The results has shown that the efficient operation of the LED can occur within the lowest current of 0.1 mA for the 2 periods of SLS with the total emission rate displayed linearly increased. A sharp decline of internal quantum efficiency (IQE) droops close to zero despite the increasing current was significantly observed for the 2 periods of SLS, which has also resulted to operate at a low turn-on voltage of 2.5 V. However, it was found that higher than 3 periods with SLS total thickness of higher than 6 nm cause the pn junction failure with no emission.

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Carbon Nanofibers (CNFs) Synthesis on Graphene/Ni Thin Film: An Analysis on the Effect of Carrier Gas Flow Rate

2023-01-01 , Fiyatillah M. , Syarifah Norfaezah Sabki , Norzilah Abdul Halif , Kita L.K.W. , Jun H.Q. , Muhammad Asri Idris , Noraini Othman , Abd Rahim A.F.

The pursuit of high-performance materials for interconnects and electrodes in various electronic applications has led to the exploration of carbon nanotubes (CNTs)-graphene hybrid materials due to their potential to surpass copper (Cu) in terms of thermal conductivity. This study aimed to grow CNTs on graphene. However, the applied growth parameters led to the formation of carbon nanofibers (CNFs) on graphene. CNFs-graphene hybrids may have lower thermal conductivity compared to CNTs-graphene hybrids. This investigation aims to understand the growth evolution of the CNFs at a varied carrier gas flow rate. This work investigates the CNFs' growth on graphene on a nickel (Ni) thin film substrate under a growth temperature of 860°C in 2 hours. By varying the gas flow rate, this research aims to discern the optimal conditions for achieving controllable CNFs growth on graphene. This work found that the higher carrier gas flow rate led to better formation of CNFs with a more uniform coverage and smaller width. The XRD results confirm the formation of CNFs on graphene.

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Performance Analysis of a Double-Gate Junctionless Transistor with Varied Doping and Gate Underlap using Device Simulator

2021-01-01 , Afiqah Nasir N.N. , Noraini Othman , Syarifah Norfaezah Sabki , Farhanah Abd Rahim A.

In this work, the impact of doping concentrations and gate underlap towards the electrical performance of a double-gate junctionless transistor (DG-JLT) were investigated using three-dimensional device simulator. The results show that the parameter of doping concentrations (Nd) has a greater impact towards the electrical performance of the transistor as compared to the gate underlap length (Lun). This can be seen in the results of leakage current (Ioff) and Drain-Induced Barrier Lowering (DIBL), where variations in Nd causes differences as high as 5 decades to be obtained for Ioff together with significant increase in DIBL. In overall, it was found that Nd=1×1018 cm-3 provides the best results in terms of the lowest DIBL and Ioff and the highest Ion/Ioff ratio. Meanwhile, longer Lun is found to give better electrical characteristics. The results obtained in this work can be used to further determine the most significant factors among the structural and material parameters that influence the electrical characteristics of a JLT.

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Numerical simulations of innovative ground plane and double-gate configurations in thin-body and -buried oxide of SOI MOSFETS

2017 , Noraini Othman

The downscaling of transistors enables an increased in transistor density, faster switching speeds and greater complexity with no increase in power consumption. However, the scaling of the conventional planar MOS transistors appears to be reaching the end of the technology roadmap due to worsening performance variability and shortchannel effects (SCEs). One of the contenders anticipated to replace the current transistor architecture is planar ultra-thin body and BOX (UTBB) SOI MOSFET. The advantage of the thin-body SOI structure lies in its simple planar process which is fully compatible with the bulk silicon CMOS flow. In this research work, a particular attention is being given to the performance of UTBB SOI MOSFETs with its thin BOX in improving electrostatics behaviour namely of drain-induced barrier lowering (DIBL) of the thin-body as compared to thick BOX (UTB) SOI transistors for extending CMOS scalability. Subsequently, UTBB with different ground plane (GP) architectures and gate configurations (i.e. single-gate (SG) vs double-gate (DG)) are extensively studied through numerical simulations as possible candidates for the continuation of Moore‟s Law. In-depth study of the digital and analog/RF figure-of-merit (FoM) are carried out in a wide range of frequency (from 0.01 Hz to 100 GHz) in correlation with device operation mechanisms. It is discovered that an innovative GP formation made of localized GP of p-type in the substrate underneath the channel (referred herein throughout the thesis as GP-B) effectively suppress substrate depletion effects and shows better immunity against SCEs from the digital analysis viewpoint. Further improvements in the immunity against SCEs can be achieved in DG configurations where the impact of different GP architectures is amplified as compared to SG. Even though the use of DG configurations provides superior digital performance, lower current gain cut-off frequency (ft) values are produced than SG in the analog domain due to an increase of gate-to-gate capacitances (Cgg). Therefore, careful selections and trade-offs are needed when selecting a particular device structure where the results obtained in this research work contribute to the identifications of GP architectures and gate configurations (SG or DG) that can be adopted in device design to suit specific applications of either digital or RF.

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A controlled growth of carbon nanofibers (CNFs) on graphene

2023-12 , Mishtha Fiyatillah , Syarifah Norfaezah Sabki , Norzilah Abdul Halif , L K Wisnu Kita , Muhammad Asri Idris , Noraini Othman , A F Abd Rahim

Carbon nanofibers (CNFs) have superior properties such as high conductivity, good mechanical strength, high specific surface area, and chemical stability. CNFs-graphene hybrid material can be used as a high-quality electrode in electronics applications. In the CNFs on graphene synthesis, the growth parameters must be well controlled. This work observes the evolution of the CNF's growth on graphene on Ni at reaction temperatures of 800oC and 860oC and at different reaction times of 30 min, 60 min, and 120 min. This research aims to find suitable conditions for obtaining controllable growth of CNFs on graphene. Based on the SEM measurement, it was found that the 860oC reaction temperature at 60 min and 120 min reaction time led to longer and smaller widths of CNFs with high coverage and distribution on graphene. The CNFs on graphene formation were confirmed by the XRD analysis.

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A Review: Synthesis and Mechanism of Growth of the Carbon Nanotubes (CNTs) – Graphene Hybrid Material and its Application as Electrodes

2023-07-01 , Mishthafiyatillah , Syarifah Norfaezah Sabki , Norzilah Abdul Halif , Muhammad Asri Idris , Noraini Othman

The CNTs–graphene hybrids have many advantages and potential for use in a wide range of electronic applications as electrodes. The CNTs–graphene hybrid structure outperforms the structure of each material in terms of characteristics and performance. There are several methods to grow CNTs. This paper reviews the chemical vapor deposition (CVD) method used to synthesize CNTs–graphene hybrid material. This paper discusses the processes and growth parameters of the synthesis of the CNTs-graphene hybrid. This paper also discusses the growth mechanism and kinetics of CNTs. In addition, the potential and performance of CNTs–Graphene hybrid material as electrodes in batteries are also reviewed.

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