Rizalafande Che Ismail
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Rizalafande Che Ismail
Official Name
Rizalafande, Che Ismail
Alternative Name
Ismail, Rizalafande C.
Rizalafande, Che Ismail
Chesmail, R.
Ismail, R. C.
Che Ismail, Rizalafande
Ismail, Rizalafande Che
Ismail, R. Che
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Scopus Author ID
22634128600

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  • Publication
    Arithmetic addition and subtraction function of logarithmic number system in positive region: An investigation
    ( 2015)
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Ali Yeon Md Shakaff
    Logarithmic number system or LNS has become an optimal choice in digital image processing instead of floating point (FP) system based on latest researches in LNS. Digital image processing which deals with a lot of complex operations such as multiplication and division, makes LNS as a great choice of implementation. However, the implementation had been restricted by the addition and subtraction function in LNS arithmetic as these functions entail complex procedures and circuitry. As its huge potential to be a substitution of FP, there is an urgent need for LNS to improve the performance of both operations. Hence, various studies had been conducted in this area, however most of the research concern the implementation of these operations in the negative region. Therefore, this study is conducted with the objective on the exploration of both LNS addition and subtraction operations in the positive region and highlights the potential areas for design modifications and improvements. Then, these enhancements will be combined with other arithmetic functions in creating an optimum LNS design to be utilized in any digital image processing system.
  • Publication
    An Analysis of Interpolation Implementation for LNS Addition and Subtraction Function in Positive Region
    ( 2016)
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Ali Yeon Md Shakaff
    Interpolation is among of the most popular approach used in approximating the values in logarithmic number system (LNS) arithmetic design. This method that often combines with lookup tables (LUTs) manages to produce efficient LNS design in area, latency and accuracy. Current research proves that the combination of interpolators with co-transformation in LNS subtraction had shown extreme improvements in terms of speed and area, which is comparable to floating point (FLP) performance. Taking the advantage, this research had been conducted to analyze the implementation of these three interpolators, which are Taylor, Lagrange and modified Lagrange, in a 32-bit environment of the LNS addition and subtraction procedures with the first-order co-transformation in positive region. The designs were analyzed in two categories, which are the accuracy towards FLP and the total memory consumption. The best interpolator was selected based on the most optimum area consumption design with manageable accuracy in FLP limit. The outcome of this analysis could benefit further improvements in LNS design.
  • Publication
    Hybrid logarithmic number system arithmetic unit: A review
    ( 2013)
    Rizalafande Che Ismail
    ;
    M.K Zakaria
    ;
    Sohiful Anuar Zainol Murad
    Logarithmic number system (LNS) arithmetic has the advantages of high performance and high-precision in complex function computation. However, the large hardware problem in LNS addition/subtraction computation has made the large word-length LNS arithmetic implementation impractical. In this paper, the concept of merging the LNS and Floating Point (FLP) operation into a single arithmetic logic unit (ALU) that can execute addition/subtraction and division/multiplication more faster, precise and less complicated has been reviewed. The advantages of using hybrid system were highlighted while comparing and explaining about FLP and LNS.
  • Publication
    Implementation of LNS addition and subtraction function with co-transformation in positive and negative region: A comparative analysis
    ( 2016)
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Ali Yeon Md Shakaff
    The European Logarithmic Microprocessor (ELM) had been an outstanding breakthrough in logarithmic number system (LNS) research history. The processor successfully reaches the par ability of floating-point (FLP) processor with its rapid and accurate design towards FLP. The design was able to improve the LNS addition and subtraction procedure, which are the drawbacks of any implementation of LNS arithmetic. ELM's subtraction operation had adopted a unique approach, which is the first-order co-transformation to overcome the singularity-to-zero issue of the non-linear function in negative region. Therefore, this research had been introduced to extensively compare and analyze the ELM-based addition and subtraction procedures with the same co-transformation technique implemented in positive region. In achieving this, two aspects are considered, which are the accuracy towards FLP and the memory consumption of both procedures in both regions. Conclusively, the exact ELM-based implementation in positive region of both operations could be realized and achieved comparable accuracy and memory area with a slight modification of the operation procedure. The outcome of this analysis could benefit further investigation of optimizing the LNS design for hardware implementation.
  • Publication
    Implementation of LNS addition and subtraction function with co-transformation in positive and negative region: A comparative analysis
    ( 2017-01-03)
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Ali Yeon Md Shakaff
    The European Logarithmic Microprocessor (ELM) had been an outstanding breakthrough in logarithmic number system (LNS) research history. The processor successfully reaches the par ability of floating-point (FLP) processor with its rapid and accurate design towards FLP. The design was able to improve the LNS addition and subtraction procedure, which are the drawbacks of any implementation of LNS arithmetic. ELM's subtraction operation had adopted a unique approach, which is the first-order co-transformation to overcome the singularity-to-zero issue of the non-linear function in negative region. Therefore, this research had been introduced to extensively compare and analyze the ELM-based addition and subtraction procedures with the same co-transformation technique implemented in positive region. In achieving this, two aspects are considered, which are the accuracy towards FLP and the memory consumption of both procedures in both regions. Conclusively, the exact ELM-based implementation in positive region of both operations could be realized and achieved comparable accuracy and memory area with a slight modification of the operation procedure. The outcome of this analysis could benefit further investigation of optimizing the LNS design for hardware implementation.
  • Publication
    LNS with Co-Transformation Competes with Floating-Point
    ( 2016)
    J. NicholasColeman
    ;
    Rizalafande Che Ismail
    The logarithmic number system has been proposed as an alternative to floating-point arithmetic. Multiplication, division and square-root operations are accomplished with inexpensive fixed-point methods, but addition and subtraction are considerably more challenging. Recent work has demonstrated that these operations too can be done with similar speed and accuracy to their FP equivalents, but the necessary circuitry is complex. In particular, it is dominated by the need for large ROM tables for the storage and interpolation of non-linear functions. We describe a new co-transformation procedure that eliminates much of the ROM space and allows the easy synthesis of the remainder in logic, and we then evaluate several interpolation methods that might benefit from it. Synthesised 32-bit implementations are compared with floating-point units, and show substantial reductions in delay, with equivalent accuracy and area.
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