Rizalafande Che Ismail
Thumbnail Image
Preferred name
Rizalafande Che Ismail
Official Name
Rizalafande, Che Ismail
Alternative Name
Ismail, Rizalafande C.
Rizalafande, Che Ismail
Chesmail, R.
Ismail, R. C.
Che Ismail, Rizalafande
Ismail, Rizalafande Che
Ismail, R. Che
Main Affiliation
Scopus Author ID
22634128600

Research Output

Filters

2
2
Reset filters

Settings
Now showing 1 - 2 of 2
  • Publication
    Analysis of FXP adders and multipliers for speed- and area-efficient LNS arithmetic unit
    ( 2014)
    Rizalafande Che Ismail
    ;
    Siti Zarina Md Naziri
    ;
    Sohiful Anuar Zainol Murad
    ;
    J. N. Coleman
    This paper portrays the selection of hardware unit architectures to be implemented in the new LNS based on a 32bit system. The implementations of the LNS multiply and divide only require a FXP adder, while the LNS addition and subtraction function comprised of several memories, FXP adders and multipliers together with other supporting logics. Thus, in choosing the best FXP adders and multipliers, each of the arithmetic is functionally verified and synthesised using Synopsys Design Compiler in Faraday 0.18 μm CMOS technology based on a 32-bit system. Two types of performance measurement, which are the worst-case delay and the silicon area, are chosen as the evaluation arguments. From conducted analytical studies, the CLA/CSLA adder and Booth recoded with Wallace tree multiplier were the best FXP adder and multiplier blocks to be applied in the system since they were the fastest designs. Using these blocks, the synthesis of the LNS system produced an approximately 7.10 ns of critical delay for addition and subtraction, and solely 1.16 ns for multiplication and division. The total area for a complete LNS architecture was 599,871 μm2, in which 65% the size of previously designed LNS architecture of ELM. © 2014 IEEE.
      26  2
  • Publication
    LNS with Co-Transformation Competes with Floating-Point
    ( 2016)
    J. NicholasColeman
    ;
    Rizalafande Che Ismail
    The logarithmic number system has been proposed as an alternative to floating-point arithmetic. Multiplication, division and square-root operations are accomplished with inexpensive fixed-point methods, but addition and subtraction are considerably more challenging. Recent work has demonstrated that these operations too can be done with similar speed and accuracy to their FP equivalents, but the necessary circuitry is complex. In particular, it is dominated by the need for large ROM tables for the storage and interpolation of non-linear functions. We describe a new co-transformation procedure that eliminates much of the ROM space and allows the easy synthesis of the remainder in logic, and we then evaluate several interpolation methods that might benefit from it. Synthesised 32-bit implementations are compared with floating-point units, and show substantial reductions in delay, with equivalent accuracy and area.
      1  14