Ramzan Mat Ayub
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Preferred name
Ramzan Mat Ayub
Official Name
Ramzan, Mat Ayub
Alternative Name
Mat Ayub, R.
Ayub, R. Mat
Ayub, R. M.
Ayub, Rm
Main Affiliation
Scopus Author ID
21741780500

Research Output
Now showing 1 - 3 of 3
  • Publication
    Numerical Simulation on the Impact of Back Gate Voltage in Thin Body and Thin Buried Oxide of Silicon on Insulator (SOI) MOSFETs
    ( 2023-10-01)
    Koay K.Y.
    ;
    Mohamad Faris Mohamad Fathil
    ;
    Mohammad Nuzaihan Md Nor
    ;
    Ramzan Mat Ayub
    ;
    Mohd Khairuddin Md Arshad
    Silicon-on-Insulator (SOI) technology provides a solution for controlling Short-Channel Effects (SCEs) and enhancing the performance of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). However, scaling down SOI MOSFETs to a nanometer scale does not necessarily yield further scaling benefits. Introducing multiple gates, such as a double gate configuration, can effectively mitigate SCEs. Nonetheless, fabricating a flawless double gate structure is an exceedingly challenging endeavor that remains unrealized. The adoption of a back gate bias, with an asymmetrical thickness arrangement between the front and back gates, mimicking the behavior of a double gate, offers an alternative approach. This approach has the potential to modify the electrical characteristics of the device, thus potentially leading to improved control over SCEs. In this study, we employed 2D simulations using Atlas to investigate the influence of back gate biases, namely,-2.0 V, 0 V, and 2.0 V on a 10 nm silicon thickness at the top and a 20 nm buried oxide thickness for n-channel MOSFETs. We focused on key parameters, including threshold voltage (VTh), Drain Induced Barrier Lowering (DIBL), and Subthreshold Swing (SS). The results demonstrate that a negative back gate bias is the most favorable configuration, as it yields superior performance. This translates into more effectively controlled SCEs across all the parameters of interest.
  • Publication
    Electrical simulation on silicon nanowire field-effect transistor biosensor at different substrate-gate voltage bias conditions for charge detection
    ( 2022-12)
    X.Y. Teoh
    ;
    Mohamad Faris Mohamad Fathil
    ;
    Y.M.Tan
    ;
    Norhayati Sabani
    ;
    Mohammad Nuzaihan Md Nor
    ;
    Mohd Khairuddin Md Arshad
    ;
    Ruslinda A. Rahim
    ;
    Nur Hamidah Abdul Halim
    ;
    Ramzan Mat Ayub
    ;
    Uda Hashim
    ;
    M.M. Ibrahim
    In this work, the impact of different substrate-gate voltage bias conditions (below and above the device threshold voltage) on current-voltage characteristics and sensitivity of a silicon nanowire field-effect transistor (SiNW-FET) biosensor was investigated. A 3-dimensional device structure with n-type SiNW channel and a substrate gate electrode was designed and electrically simulated In the Silvaco ATLAS. Next, the SiNW channel was covered with a range of interface charge density to mimic the charged target biomolecule captured by the device. The outcome was translated into a drain current versus interface charge semi-log graph and the device sensitivity was calculated using the linear regression curve’s slope of the plotted data. The device’s electrical characteristic shown higher generation of output drain current values with the increase of negative substrate-gate voltage bias due to the hole carriers’ accumulation that forms a conduction channel in the SiNW. Application of higher negative interface charge density increased the change in drain current, with the device biased with higher substrate-gate voltage shows more significant change in drain current. The device sensitivity increased when biased with higher substrate-gate voltage with highest sensitivity is 75.12 nA/dec at substrate-gate voltage bias of –1.00 V.
      2  17
  • Publication
    Numerical simulation on the impact of back gate voltage in thin body and thin buried oxide of silicon on insulator (SOI) MOSFETs
    ( 2023-10)
    K.Y Koay
    ;
    Mohamad Faris Mohamad Fathil
    ;
    Mohammad Nuzaihan Md Nor
    ;
    Ramzan Mat Ayub
    ;
    Mohd Khairuddin Md Arshad
    Silicon-on-Insulator (SOI) technology provides a solution for controlling Short-Channel Effects (SCEs) and enhancing the performance of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). However, scaling down SOI MOSFETs to a nanometer scale does not necessarily yield further scaling benefits. Introducing multiple gates, such as a double gate configuration, can effectively mitigate SCEs. Nonetheless, fabricating a flawless double gate structure is an exceedingly challenging endeavor that remains unrealized. The adoption of a back gate bias, with an asymmetrical thickness arrangement between the front and back gates, mimicking the behavior of a double gate, offers an alternative approach. This approach has the potential to modify the electrical characteristics of the device, thus potentially leading to improved control over SCEs. In this study, we employed 2D simulations using Atlas to investigate the influence of back gate biases, namely, -2.0 V, 0 V, and 2.0 V on a 10 nm silicon thickness at the top and a 20 nm buried oxide thickness for n-channel MOSFETs. We focused on key parameters, including threshold voltage (VTh), Drain Induced Barrier Lowering (DIBL), and Subthreshold Swing (SS). The results demonstrate that a negative back gate bias is the most favorable configuration, as it yields superior performance. This translates into more effectively controlled SCEs across all the parameters of interest.
      1  7