High performance 32-bit logarithmic number system for non-linear arithmetic operations

In a computer arithmetic, a straightforward algebraic property of a logarithmic number system (LNS) towards the multiplication and division are of importance. An improvised version of a LNS is needed since the non-linear computations at the addition and subtraction represent significant challenges. In addition, the complex function of the subtraction caused by singularity requires an enormous size of memory. This thesis focuses on the improvisation of two algorithms, namely the co-transformation and interpolation for a high performance 32-bit arithmetic unit. For the co-transformation procedure, the singularity region covered by the previous architecture is optimized to reduce the latency. Meanwhile, assorted interpolation schemes in addition and subtraction operations are also evaluated for a compact lookup table (LUT) to give a rapid and an accurate computation. The evaluation in this research work reveals an optimized LNS architecture with a double co-transformation technique which has an averagely 47% faster speed when it is benchmarked against the recent LNS design. From the proposed hybrid interpolation scheme, the speed and area of the new LNS design are found to be far more superior than the existing LNS design and are also on par with the recent floating-point (FLP) design. The amount of memory which is dominated by the co-transformation architecture can also be reduced. The proposed system is synthesized by selecting a Ladner Fisher (LF) adder as well as a Booth with Wallace Tree multiplier to boost the computation speed. It is found that the proposed system is able to provide an economical area with rapid computation while sustaining the accuracy better than the floating-point (BTFP), which is in agreement with the benchmarking results made against the previous logarithm number and floating-point units.