Design of high-efficiency CMOS Class E power amplifier with active inductor for 5G applications

5G technology has made huge advancements in the past few years, especially in the speeds and applications. They have much faster speeds compared to 4G technology. These applications require components in their transceiver system, which can transmit and receive information through a network. One of those components is the power amplifier (PA), a device that can amplify the signal. However, the efficiency of power amplifiers is limited at high frequencies. The reduction in the efficiency of the device mainly happens because of the low Q-factor of the components that make up the design of the circuit. The worst contributing factors are the on-chip inductors, which can occupy a significant amount of area and have the greatest impact on the device due to their low Q-factor. The low Q-factor affects efficiency due to the high losses from the on-chip spiral inductors. The objective of this research is to design high power added efficiency (PAE) of PA to enhance the performance of the overall transceiver. Therefore, a high-quality active inductor (AI) is proposed to replace the spiral inductor in PA circuit to reduce losses and thus increase the efficiency of PA. The proposed active inductor employed a fully differential structure with a cascode current mirror. The AI is designed and simulated in Cadence Virtuoso using Silterra CMOS 0.18 μm technology. Further, the proposed AI is integrated with a class E PA. Class E PA consists of two stages, which are a driver stage and a class E power stage. The post layout simulation shows that the active inductor achieves a high-quality factor of 16,000 at 3.0 GHz frequency, however the Q factor is reduced to 500 at the targeted frequency of 3.5 GHz. The Q factor at targeted frequency at 3.5 GHz is still reasonable to reduce the losses. Furthermore, the active inductor is added to the output matching network of PA to replace the on-chip spiral inductor. The pre-layout simulation results indicate that the PAE is increased from 67.33 % to 75.75 % when spiral inductor is replaced by AI. Similarly, the PAE increased to 63.88 % from 50.6 % in a post-layout simulation. The discrepancy between pre and post layout is due to the parasitic effects.