This paper proposes a design of a low-power operational ampliér (op-amp) for pipeline analog-to-digital converter (ADC) applications using a 0.13-μm CMOS process. The folded-cascode topology with NMOS input types is employed for the op-amp design due to a larger output gain compared to PMOS input types. Furthermore, the op-amp is designed with a double detection structure of a common-mode feedback circuit to provide stable feedback voltage. The simulation results show that the proposed op-amp achieved a gain of 64.5 dB and a unity gain bandwidth of 695.1 MHz with a low power consumption of 0.14 mW. In addition, by applying ±1.2 V of input voltage, the output voltage generated by the proposed op-amp design remains at 1.2 V with a constant feedback voltage of 1.3 V. Moreover, the proposed circuit was implemented and simulated successfully in a 1.5-bit per stage pipeline ADC.
