Comprehensive study on gate recess step for the fabrication of high-speed InGaAs/InAlAs/InP pHEMT

We report a comprehensive etching study on the gate recess step for the fabrication of the novel high speed pHEMT devices. The experiments focused on the elimination of 'hump' structure as a result of an incomplete etching process at the InGaAs cap layer. In this work, two types of test samples were used, namely bulk InGaAs and epitaxial structure together with an etch stop layer. The result showed that the etch rate of bulk InGaAs is about 360 A/min and the percentage of dome height is consistent at approximately 25%. Meanwhile, the study on pHEMT epitaxial layer showed that the etching time of 3 minutes is sufficient in order to completely remove the cap layer. Gate leakage current of magnitude more than 10 times lower is observed on the devices that engaging Succinic Acid as the gate recess etching agent. The optimized processing steps will tailor for highly reproducible pHEMT fabrication process for high speed applications.