Mohd Nazrin Md Isa

Preferred name

Mohd Nazrin Md Isa

Official Name

Mohd Nazrin , Md Isa

Alternative Name

Md Isa, Mohd N.

Isa, M. Nazrin Md

Md Isa, M. N.

Isa, Nazrin

Isa, M. Nazrin M.

Main Affiliation

Universiti Malaysia Perlis

Scopus Author ID

56426995200

Researcher ID

N-1250-2017

Research Output

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Speed and Area Efficient FXP Adders and Multipliers: A Comparative Analysis for LNS System

( 2020-12-18)
Basir M.S.S.M.
;
Rizalafande Che Ismail
;
Siti Zarina Md Naziri
;
Mohd Nazrin Md Isa
;
Sohiful Anuar Zainol Murad
;
Azizi Harun

In this paper, a variety of adder and multiplier are compared to be implemented in a new logarithmic number system (LNS). Both adder and multiplier are designed with a generic very high-speed integrated circuit hardware description language (Verilog) program. This makes it possible to achieve the optimum performance in latency and area of 0.18µm CMOS technologies LNS chip. Consequently, the optimal configurations vary with speed and area of the schemes and in some cases can be compact area, O(n), fast in latency O(log2 n) or optimized. The program was scripted based on fixed-point (FXP) adders and multipliers that yet will be implemented in LNS system. The functionality of the scheme was tested before synthesized. Outcomes show that Ladner Fisher (LF) adder and modified Baugh Wooley multiplier contribute to fast in latency and consume minimal area.

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