Ramzan Mat Ayub
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Preferred name
Ramzan Mat Ayub
Official Name
Ramzan, Mat Ayub
Alternative Name
Mat Ayub, R.
Ayub, R. Mat
Ayub, R. M.
Ayub, Rm
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Scopus Author ID
21741780500

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FET with underlap structure for biosensing applications

2018-01 , Claris C. J. W , Mohd Khairuddin Md Arshad , C. Ibau , Ramzan Mat Ayub , Mohamad Faris Mohamad Fathil , Norhaimi W. M. W.

This paper presents the numerical simulation of an underlap field effect transistor (FET) device architecture on silicon‐on‐insulator (SOI) substrate for biosensing applications. By using the Silvaco ATLAS device simulator, this work is aimed to elucidate the effects of the different gate lengths, the presence of interface charge on the underlap sensing region, and also the effects of different gate biases (i.e. singlegate biasing, synchronous doublegate biasing and asynchronous doublegate biasing) on the magnitude of drain current (ID) of the simulated device. It is found that shorter gate length with the positive charges (on the n‐p‐n structure), at the sensing channel area increased the electron concentration at the channel and substrate/buried oxide interface. In asynchronous doublegate with a +3V of back‐gate supply and synchronous double‐gate, both increased the ID at different magnitude level and off‐current. Thus, depending on the biomolecule charges, the substrate biasing can be altered to improve the device’s sensitivity.

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Electrical simulation on silicon nanowire field-effect transistor biosensor at different substrate-gate voltage bias conditions for charge detection

2022-12 , X.Y. Teoh , Mohamad Faris Mohamad Fathil , Y.M.Tan , Norhayati Sabani , Mohammad Nuzaihan Md Nor , Mohd Khairuddin Md Arshad , Ruslinda A. Rahim , Nur Hamidah Abdul Halim , Ramzan Mat Ayub , Uda Hashim , M.M. Ibrahim

In this work, the impact of different substrate-gate voltage bias conditions (below and above the device threshold voltage) on current-voltage characteristics and sensitivity of a silicon nanowire field-effect transistor (SiNW-FET) biosensor was investigated. A 3-dimensional device structure with n-type SiNW channel and a substrate gate electrode was designed and electrically simulated In the Silvaco ATLAS. Next, the SiNW channel was covered with a range of interface charge density to mimic the charged target biomolecule captured by the device. The outcome was translated into a drain current versus interface charge semi-log graph and the device sensitivity was calculated using the linear regression curve’s slope of the plotted data. The device’s electrical characteristic shown higher generation of output drain current values with the increase of negative substrate-gate voltage bias due to the hole carriers’ accumulation that forms a conduction channel in the SiNW. Application of higher negative interface charge density increased the change in drain current, with the device biased with higher substrate-gate voltage shows more significant change in drain current. The device sensitivity increased when biased with higher substrate-gate voltage with highest sensitivity is 75.12 nA/dec at substrate-gate voltage bias of –1.00 V.

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Numerical Simulation on the Impact of Back Gate Voltage in Thin Body and Thin Buried Oxide of Silicon on Insulator (SOI) MOSFETs

2023-10-01 , Koay K.Y. , Mohamad Faris Mohamad Fathil , Mohammad Nuzaihan Md Nor , Ramzan Mat Ayub , Mohd Khairuddin Md Arshad

Silicon-on-Insulator (SOI) technology provides a solution for controlling Short-Channel Effects (SCEs) and enhancing the performance of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). However, scaling down SOI MOSFETs to a nanometer scale does not necessarily yield further scaling benefits. Introducing multiple gates, such as a double gate configuration, can effectively mitigate SCEs. Nonetheless, fabricating a flawless double gate structure is an exceedingly challenging endeavor that remains unrealized. The adoption of a back gate bias, with an asymmetrical thickness arrangement between the front and back gates, mimicking the behavior of a double gate, offers an alternative approach. This approach has the potential to modify the electrical characteristics of the device, thus potentially leading to improved control over SCEs. In this study, we employed 2D simulations using Atlas to investigate the influence of back gate biases, namely,-2.0 V, 0 V, and 2.0 V on a 10 nm silicon thickness at the top and a 20 nm buried oxide thickness for n-channel MOSFETs. We focused on key parameters, including threshold voltage (VTh), Drain Induced Barrier Lowering (DIBL), and Subthreshold Swing (SS). The results demonstrate that a negative back gate bias is the most favorable configuration, as it yields superior performance. This translates into more effectively controlled SCEs across all the parameters of interest.

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Numerical simulation on the impact of back gate voltage in thin body and thin buried oxide of silicon on insulator (SOI) MOSFETs

2023-10 , K.Y Koay , Mohamad Faris Mohamad Fathil , Mohammad Nuzaihan Md Nor , Ramzan Mat Ayub , Mohd Khairuddin Md Arshad

Silicon-on-Insulator (SOI) technology provides a solution for controlling Short-Channel Effects (SCEs) and enhancing the performance of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). However, scaling down SOI MOSFETs to a nanometer scale does not necessarily yield further scaling benefits. Introducing multiple gates, such as a double gate configuration, can effectively mitigate SCEs. Nonetheless, fabricating a flawless double gate structure is an exceedingly challenging endeavor that remains unrealized. The adoption of a back gate bias, with an asymmetrical thickness arrangement between the front and back gates, mimicking the behavior of a double gate, offers an alternative approach. This approach has the potential to modify the electrical characteristics of the device, thus potentially leading to improved control over SCEs. In this study, we employed 2D simulations using Atlas to investigate the influence of back gate biases, namely, -2.0 V, 0 V, and 2.0 V on a 10 nm silicon thickness at the top and a 20 nm buried oxide thickness for n-channel MOSFETs. We focused on key parameters, including threshold voltage (VTh), Drain Induced Barrier Lowering (DIBL), and Subthreshold Swing (SS). The results demonstrate that a negative back gate bias is the most favorable configuration, as it yields superior performance. This translates into more effectively controlled SCEs across all the parameters of interest.

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Lectin bioreceptor approach in capacitive biosensor for prostate-specific membrane antigen detection in diagnosing prostate cancer

2021-03-01 , Subramani I.G. , Ramzan Mat Ayub , Subash Chandra Bose Gopinath , Perumal V. , Mohamad Faris Mohamad Fathil , Mohd Khairuddin Md Arshad

This research reports a new approach with lectin-based capacitive non-faradaic biosensor for the detection of prostate-specific membrane antigen (PSMA) as a promising diagnostic marker for determining prostate cancer. PSMA expression is significantly higher in malign hyperplasia, thus can be effectively employed to discriminate other benign prostatic diseases. Herein, the aluminium interdigitated electrode was fabricated and modified by a linker, 2-mercaptoacetate to form the self-assembled monolayer. Gold nanoparticles were used as a signal amplifier and supported the conjugation of Concanavalin A, for efficient capacitive sensing of PSMA. Scanning electron microscope observation effectively captured the surface modification on the aluminium surface by revealing the specific adherence of gold nanoparticles with Concanavalin A. Moreover, the successful surface modification was further validated by atomic force microscopy, Fourier transforms infrared spectroscopy, and X-ray photoelectron spectroscopy. The interaction analysis of Concanavalin A with PSMA by capacitive non-faradaic measurement exhibited a linear detection range from 10 pM to 100 nM and attained the detection limit and sensitivity of 10 pM and 1.65 nF/pM respectively as the comparable performance to the current sensing strategies. Furthermore, the fabrication and quantification of PSMA as demonstrated here are relatively simple and can be employed for the straightforward detection of other biomarkers.

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Fabrication and chracterization of single and multilayer tunnel dielectrics for advanced floating gate flash memory

2014 , Ramzan Mat Ayub

The floating gate device has been the workhorse for the non-volatile memory technology since the beginning of flash memory era. However, as the device is scaled down towards the realms of nanometer dimension, floating gate flash faces a very steep scaling path. The tunnel oxide scaling has a practical limit of approximately 8 nm due to data retention requirement. Therefore, the purpose of this work is to characterize and to assess the performances of single and multi-layer tunnel oxide, which primary focus is to further scale it beyond 8 nm. This study was carried out in two steps. Firstly, device I-V characteristics were simulated using the MATLAB software, based on the most recent compact physical model. Programming speed and data retention were calculated based on the simulated I-V curves. Secondly, MOS capacitors were then fabricated and characterized to validate the simulation result. The performance of single layer tunnel oxide has been successfully demonstrated. Its performance has been mainly evaluated from two perspectives, namely the programming time τprog, and data retention τret. The τprog for 4 nm single layer oxide and oxynitride were calculated to be 110 μs and 130 μs respectively, not too far off from 100 μs technological requirement. However, their τret performance was well below 10-year requirement, with both dielectrics just been able to achieve 3.1 and 4.6 year respectively. In that sense, one can conclude that both 4 nm single layer oxide and oxynitride have failed to comply with the requirement of 18 nm technology node. However, it has been proved that nitrided oxide could improve the τret of single layer SiO2. Furthermore, it has also been demonstrated that the thickness of a single layer oxide and oxynitride of 8.25 and 6.4 nm respectively, would be required to achieve the 10-year data retention requirement. It has also been shown that nitrided oxide could serve as an effective way of suppressing trap generation which in turn would suppress low field device leakages, especially in the form of SILC. In the case of multi-layer dielectrics, it has been shown that the best configuration is the one with the thinnest bottom SiO2 / thickest Si3N4. Device simulation shows that for 2 and 3-layer dielectrics, the τprog was in the range of 18 to 41 μs for the EOT of 4 to 8 nm, while experimentally it’s in the range of 2 to 104 μs. Taking τret requirement into consideration however reveals that only configurations with the EOT of 6 nm for both 2 and 3-layer dielectrics and 8 nm of 3-layer dielectric have successfully met the requirement for 18 nm technology nodes.

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