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  1. Home
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  5. Digital Piano Keyboard Design using FPGA Implementation for Beginner
 
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Digital Piano Keyboard Design using FPGA Implementation for Beginner

Journal
IOP Conference Series: Materials Science and Engineering
ISSN
17578981
Date Issued
2020-09-21
Author(s)
Asyraf Khairuddin M.A.
Universiti Tun Hussein Onn Malaysia
Ahmad N.
Universiti Tun Hussein Onn Malaysia
Helmy Abd Wahab M.
Universiti Tun Hussein Onn Malaysia
Syed Zulkarnain Syed Idrus
Universiti Malaysia Perlis
DOI
10.1088/1757-899X/917/1/012053
Handle (URI)
https://iopscience.iop.org/article/10.1088/1757-899X/917/1/012053
Abstract
With the future technology and architecture, the digital musical instruments have been designed into a pack of electronic hardware and software with no strings or animal skins for producing an instruments sound. One of the musical instruments with high interest to learn by a beginner is piano. To solve this problem, this research aimed to design and development of basic digital piano keyboard using FPGA for rapid prototyping. The core of this project is keynotes which is a common input peripheral device that is connected with FPGA which is DE1-SoC-MTL2 and speaker to complete a basic learning system of piano. The architecture is designed using Verilog HDL through the Altera Quartus Prime software. Verilog has been designed to export every 13 keys to 13 certain note then implemented on DE1-SoC-MTL2. The basic system process is a keynote press is needed to activate or produce the certain piano sound. MTL2 used to display a pressed keynote. There are 13 keys in total of piano keynotes for this design where each key represents a different note or frequency to match the existing piano at the present day. The 13 different notes are low octave C, C#, D, D#, E, F, F#, G#, A#, B and high octave C basically for beginner user knowledge. All the components of the system are verified using oscilloscope. This digital piano keyboard designed on FPGA has been implemented for user beginner needs, who want to learn to play piano at very basic stage.
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