A novel energy efficient of network on-chip (NoC) architecture for system on-chip (SoC)

As the number of intellectual property (IP) integrated into a chip increases, this can present serious challenges to achieving the performance and power needed for satisfying the constraint on future chip. The addition of the intelligent networking on the chip adds to the power consumption of network-on-chip (NoC). Thus, system-on-chip (SoCs) is required to be capable of delivering high performance and consuming low power, of the interconnection infrastructure to large number of cores. This research aims to focus on proposing ways to use current available network interconnection modal to provide NoC of better performance, smaller total area, and higher power efficiency, by optimizing interconnection architecture. In order to solve the problem encountered with large scale network, a design of power saving clustering, segmentation-connectivity, and partition technique is useful for multiple homogeneous applications which need to be executed in parallel and mapped on a large network. This technique reduces the number of link and lowers the average distance of a network, which help in achieving low power consumption. Topology can be clustering, segmenting, and partitioning the cores of similar characteristic into the same group. The nodes in the same group are highly connected, while the nodes in different group are sparsely connected. The objective of research is to search for the most power efficient and performance aware topologies based on clustering, segmentation-connectivity, and partition strategy. At the same time, this research minimizes performance penalty by applying sleep mode, standby mode, and hibernation mode based on different runtime application. This is crucial as different application has different requirement of logical cluster, segment, and partition size. By efficiently handling the connection of clustering, segmentation-connectivity, and partition technique, the experimental results show that these techniques achieve up to 9.39% ~ 71.89% power saving, up to 0.97% ~ 53.59% area saving; reduce average network latency up to 9.81% ~ 76.26%; and up to 6.65% ~ 78.96% power latency product (PLP) saving as compared to traditional topology. In the end, the results show that turning ‘off’ the nodes of the cluster, segment, and partition topologies reduce latency and power consumption. The results also indicate the importance of power and latency co-optimization in NoC design.