Simulation of graphene band structure and fabrication of graphene field effect transistor

This thesis presents an approach in exploring graphene for digital electronics, as well as analogues. For digital electronic application, this work focused on opening and tuning the monolayer graphene band gap based on the inclusion of dopant atoms, by using AtomixKit Simulator from Quantum Wise. Two sets of simulation have been carried out, that are, to study the graphene band structures based on the effect of asymmetrical bilayer graphene layers and doping the monolayer graphene with boron and Oxygen atoms. Results have shown that monolayer and symmetrical bilayer graphene exhibit zero band gaps, while asymmetrical bilayer graphene provides a band gap of 0.35 eV. The opening of energy band gap in asymmetrical hi- and multi-layer graphene is limited and reduces electron mobility. So another approach to open the band gap without disrupting the high electron mobility in monolayer graphene, is by doping the graphene. This work has shown that the inclusion of dopant atoms in monolayer graphene results in an increase in the band gap, with increased number of dopant atoms. The position of the dopant atoms in monolayer graphene also significantly affects the band gap opening. It is obtained that Oxygen atoms in graphene give rise to higher band gap openings compared to boron atoms. This ability to modify the monolayer graphene band gap can be applied for many digital electronic applications. For analogue application, this research focused on investigating the effect of channel length and gate oxide thickness of graphene field effect transistor (GFET). This GFET fabrication required a good coverage of monolayer graphene. This work has performed an optimization in the graphene transfer process, in which a stamping method using a wooden block is suggested. A proper cleaning process in acetone is also crucial in order to obtain a good layer of graphene before GFET can be fabricated. In this work, the GFET performance is investigated based on the charge carrier mobility taken from both transportation of electrons and holes. The GFETs have been fabricated with two different gate oxides with thicknesses of 63 nm and 83 nm with channel lengths varied from 250 𝛍m to 650 𝛍m. Results have shown that the electron mobility in GFET increases as the channel lengths decreases. The same pattern is observed for hole carrier mobility. However, it is obtained that the electrons and holes mobility decreases as the gate oxide thickness increases. It can be concluded that the GFET channel length and gate oxide thickness play an important role in determining the GFET performance, as the speed of the device increases with shorter channel and thicker gate oxide.