Ultra-low power 0.45 mw 2.4 ghz cmos low noise amplifier for wireless sensor networks using 0.13-μm technology

This paper describes the design topology of a ultra-low power low noise amplifier (LNA) for wireless sensor network (WSN) application. The proposed design of ultra-low power 2.4 GHz CMOS LNA is implemented using 0.13-µm Silterra technology. The LNA benefits of low power from forward body bias technique for first and second stages. Two stages are implemented in order to enhance the gain while obtaining low power consumption for overall circuit. The simulation results show that the total power consumed is only 0.45 mW at low supply voltage of 0.55 V. The power consumption is decreased about 36% as compared with the previous work. A gain of 15.1 dB, noise figure (NF) of 5.9 dB and input third order intercept point (IIP3) of-2 dBm are achieved. The input return loss (S11) and the output return loss (S22) is-17.6 dB and-12.3 dB, respectively. Meanwhile, the calculated figure of merit (FOM) is 7.19 mW-1.