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Enhancing circuit development and layout implementation of benchmark circuit in 0.18-μm CMOS technology

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dc.contributor.author Joel Matthew Thomas Matthew
dc.contributor.author Nur Zatil Ismah Hashim
dc.contributor.author Sofiyah Sal Hamid
dc.contributor.author Nuha A. Rhaffor
dc.date.accessioned 2025-02-28T07:52:20Z
dc.date.available 2025-02-28T07:52:20Z
dc.date.issued 2025-01
dc.description.abstract Power consumption and delay are the most critical factors in circuit development and layout implementation. It is challenging to optimize all aspects simultaneously. This research addresses this challenge by analysing the power consumption and delay effects in benchmark circuit operation, C6288, using 0.18-μm CMOS technology operating at an optimal voltage of 1.6V. Additionally, this research also contributes to developing the initial layout implementation of a benchmark circuit with a 10% area reduction. By utilizing new layout techniques and simulations, the study has proven a significant decrease in power consumption and enhanced area optimization with a moderate increase in delay at 1.6V, all while maintaining acceptable performance standards. In addition, simulation results indicate less than a 10% deviation between pre- and post-layout designs. Finally, through the properties of layout design and the research conclusions, it has provided valuable insights for the design of energy-efficient digital circuits in CMOS technology.
dc.identifier.doi 10.58915/ijneam.v18i1.1679
dc.identifier.uri https://ejournal.unimap.edu.my/index.php/ijneam/article/view/1679/1043
dc.identifier.uri https://hdl.handle.net/20.500.14170/13713
dc.language.iso en
dc.relation.ispartof International Journal of Nanoelectronics and Materials (IJNeaM)
dc.relation.issn 1985-5761
dc.subject Layout implementation
dc.subject Benchmark circuit
dc.subject Power consumption
dc.subject Delay effects area optimization
dc.subject CMOS technology
dc.title Enhancing circuit development and layout implementation of benchmark circuit in 0.18-μm CMOS technology
dc.type Resource Types::text::journal::journal article
dspace.entity.type Publication
oaire.citation.endPage 6
oaire.citation.issue 1
oaire.citation.startPage 1
oaire.citation.volume 18
oairecerif.author.affiliation Universiti Sains Malaysia
oairecerif.author.affiliation Universiti Sains Malaysia
oairecerif.author.affiliation Universiti Sains Malaysia
oairecerif.author.affiliation Universiti Sains Malaysia
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International Journal of Nanoelectronics and Materials (IJNeaM)