Power consumption and delay are the most critical factors in circuit development and layout implementation. It is challenging to optimize all aspects simultaneously. This research addresses this challenge by analysing the power consumption and delay effects in benchmark circuit operation, C6288, using 0.18-μm CMOS technology operating at an optimal voltage of 1.6V. Additionally, this research also contributes to developing the initial layout implementation of a benchmark circuit with a 10% area reduction. By utilizing new layout techniques and simulations, the study has proven a significant decrease in power consumption and enhanced area optimization with a moderate increase in delay at 1.6V, all while maintaining acceptable performance standards. In addition, simulation results indicate less than a 10% deviation between pre- and post-layout designs. Finally, through the properties of layout design and the research conclusions, it has provided valuable insights for the design of energy-efficient digital circuits in CMOS technology.
