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An efficient processing element architecture for pairwise sequence alignment

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cris.virtual.department Universiti Malaysia Perlis
cris.virtual.department Universiti Malaysia Perlis
cris.virtual.department Universiti Malaysia Perlis
cris.virtual.department Universiti Malaysia Perlis
cris.virtual.department Universiti Malaysia Perlis
cris.virtualsource.department 2dab9ecc-7fc7-4448-b0bf-3021c88519e2
cris.virtualsource.department fe956e29-82ee-486c-b764-d30fe182c2a9
cris.virtualsource.department c074e684-00ff-44f4-a69a-cc19c7850721
cris.virtualsource.department a19d4cbc-2489-4c8e-8287-251ae470e4c4
cris.virtualsource.department d529e9b5-30cc-47a5-a0c9-8eeee55f7c96
dc.contributor.author Mohd Nazrin Md Isa
dc.contributor.author Sohiful Anuar Zainol Murad
dc.contributor.author Rizalafande Che Ismail
dc.contributor.author Muhammad Imran Ahmad
dc.contributor.author Asral Bahari Jambek
dc.contributor.author M. K. Md Kamil
dc.date.accessioned 2024-12-01T02:47:36Z
dc.date.available 2024-12-01T02:47:36Z
dc.date.issued 2014
dc.identifier.doi 10.1109/ICED.2014.7015850
dc.identifier.uri An efficient processing element architecture for pairwise sequence alignment.pdf
dc.identifier.uri https://ieeexplore.ieee.org/xpl/conhome/6996693/proceeding
dc.identifier.uri https://hdl.handle.net/20.500.14170/9895
dc.relation.ispartof 2014 2nd International Conference on Electronic Design (ICED)
dc.title An efficient processing element architecture for pairwise sequence alignment
dc.type Resource Types::text::conference output::conference proceedings::conference paper
dspace.entity.type Publication
oaire.citation.endPage 464
oaire.citation.startPage 461
oairecerif.author.affiliation Universiti Malaysia Perlis
oairecerif.author.affiliation Universiti Malaysia Perlis
oairecerif.author.affiliation Universiti Malaysia Perlis
oairecerif.author.affiliation Universiti Malaysia Perlis
oairecerif.author.affiliation Universiti Malaysia Perlis
oairecerif.author.affiliation Universiti Malaysia Perlis
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