The modelling of SiC Gate Oxide thickness based on thermal oxidation temperatures and durations for high-voltage applications

This research has shown that the oxide thickness for silicon carbide (SiC) based wide materials can be predicted using regression techniques in wet/dry nitrided or wet/dry non-nitrided thermal oxidation process conditions for high voltage applications by employing 2 different regression techniques: Polynomial and linear regression. The R-squared (R2) and Mean Absolute Percentage Error (MAPE) techniques are used to evaluate the regression models. Furthermore, this work investigates and presents a calculation of gate oxide thickness that is correlated to gate voltage ranges for high voltage applications. In this work, the thermal oxidation process environment is classified into 3 different processing conditions: conventional (dry and wet), dry nitrided (NO,N2O), and wet nitrided (HNO3 vapour). The findings from this study showed that wet oxidation combined with nitrided elements can produce thicker and better-quality gate oxide as compared to conventional dry and wet oxidation techniques. The outcome of this work clearly shows that gate oxide thickness may be derived from silicon carbide-based wide-bandgap materials utilizing linear and polynomial approaches using thermal oxidation durations at different temperatures for high-power applications. The regression models and formulations produced in this work are expected to aid the researchers in determining appropriate oxide thickness under practicable process conditions, with the exception of real thermal oxidation process conditions. Hence, the outcome of this work is expected to save the processing time, material, and cost of the power semiconductor device fabrication technology, mainly for high voltage applications.