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  5. Five-phase multilevel inverter with reduced number of power semiconductor switches controlled using PSO-SHMPWM
 
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Five-phase multilevel inverter with reduced number of power semiconductor switches controlled using PSO-SHMPWM

Journal
AIP Conference Proceedings
ISSN
0094-243X
Date Issued
2024-02
Author(s)
W. V. Yong
Faculty of Electrical Engineering Technology, Universiti Malaysia Perlis (UniMAP)
W. T. Chew
Faculty of Electrical Engineering Technology, Universiti Malaysia Perlis (UniMAP)
Ong Siok Lan
Universiti Malaysia Perlis
Y. W. Sea
Faculty of Electrical Engineering Technology, Universiti Malaysia Perlis (UniMAP)
Leong Jenn Hwai , Jenn
Universiti Malaysia Perlis
DOI
10.1063/5.0192629
Handle (URI)
https://pubs.aip.org/aip/
https://hdl.handle.net/20.500.14170/16088
Abstract
A five-phase multilevel inverter (MI) that has a lower number of power semiconductor switches is proposed. Compared to cascaded H-bridge multilevel inverter (CHBMI), the proposed MI has a lower number of power semiconductor switches. For example, a five-phase seven-level CHBMI consists of 60 power semiconductor switches while the proposed MI has 40 power semiconductor switches, which is reduced by 20 switches or 33.33 %. The switching angles implemented to the proposed MI are obtained using selective harmonic minimization pulse-width modulation (SHMPWM) technique solved by particle swarm optimization (PSO) algorithm. Simulation is carried out using PSIM software to verify the performance of the proposed MI and the simulation results show that the proposed MI can synthesize a sinusoidal-like staircase output voltage waveform.
Subjects
  • Inverters

  • Semiconductor switch

  • Pulse width modulatio...

  • Mathematical optimiza...

File(s)
Five-phase multilevel inverter with reduced number of power semiconductor switches controlled using PSO-SHMPWM.pdf (127.3 KB)
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