Ong Siok Lan
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Preferred name
Ong Siok Lan
Official Name
Ong, Siok Lan
Alternative Name
Ong, J. S.L.
Ong, J. Siok Lan
Ong, J. S.
Ong, Jennifer S.L.
Main Affiliation
Scopus Author ID
54387344600
Researcher ID
FQE-4956-2022

Research Output

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  • Publication
    Feasibility study of seven-level two-stage cascaded switch-diode multilevel inverter under different inductive loads
    (AIP Publishing, 2024-02)
    Yong Wui Ven
    ;
    Yee Wei Sea
    ;
    Ong Siok Lan
    ;
    Leong Jenn Hwai
    Two-stage cascaded switch-diode multilevel inverter (TSCSDMI) is a modified cascaded H-bridge multilevel inverter (CHMI) with a reduced number of active power semiconductor switches. The TSCSDMI topology is constructed with two main circuit stages. The 1st stage consists of several cascaded switch-diode basic cell modules and a bypassing active power semiconductor switch, whilst the 2nd stage consists of a H-bridge module. The implementation and performance of a five-level TSCSDMI have been reported in the literature. However, the feasibility of the TSCSDMI with a higher number of voltage levels under different inductive loads has not been fully explored. Hence, this paper evaluates and analyzes the performance of seven-level TSCSDMI operating under different inductive. The analysis is conducted using PSIM simulation and the simulation results suggest that the seven-level TSCSDMI is not suitable for heavier inductive loads. For example, the output voltage waveform of seven-level TSCSDMI starts to deteriorate with an undesired voltage spike when the displacement power factor of an inductive load is equal to 0.90 or lower. The undesired voltage spike tends to worsen the total harmonic distortion (THD) of the output voltage waveform. Hence, for minimal THD operations, a seven-level TSCSDMI should be employed for applications with light inductive load.
  • Publication
    Five-phase multilevel inverter with reduced number of power semiconductor switches controlled using PSO-SHMPWM
    (AIP Publishing, 2024-02)
    W. V. Yong
    ;
    W. T. Chew
    ;
    Ong Siok Lan
    ;
    Y. W. Sea
    ;
    Leong Jenn Hwai , Jenn
    A five-phase multilevel inverter (MI) that has a lower number of power semiconductor switches is proposed. Compared to cascaded H-bridge multilevel inverter (CHBMI), the proposed MI has a lower number of power semiconductor switches. For example, a five-phase seven-level CHBMI consists of 60 power semiconductor switches while the proposed MI has 40 power semiconductor switches, which is reduced by 20 switches or 33.33 %. The switching angles implemented to the proposed MI are obtained using selective harmonic minimization pulse-width modulation (SHMPWM) technique solved by particle swarm optimization (PSO) algorithm. Simulation is carried out using PSIM software to verify the performance of the proposed MI and the simulation results show that the proposed MI can synthesize a sinusoidal-like staircase output voltage waveform.