There are varieties of image algorithms have been used to enhance images in spatial domain. The sequential implementation was used for image processing as main approach and it consume a lot of time, since images have massive data to process. Therefore, there is a necessity to use parallel approach to speed up image processing. Few technologies are used to support parallelism. Field Programming Gate Array (FPGA) is most significant technology supporting true parallelism in addition to reconfigurability potential. The proposed project is concerned with the design and
implementation of selected algorithms to enhance image features such as contrast, brightness, threshold, and invert. In this project, the parallelism features on FPGA is explored by applying spatial parallelism to build embedded real time system. A hardware and software implementation of image processing system to enhance grayscale image on spatial domain is proposed. The VHDL and megaCore modules are used to implement proposed design. The utilization of parallel on-chip registers and memory enhanced the processing time of implemented algorithms. An FPGA development Board DE2-115 is used as vehicle project. The results of implemented design show that the throughput is increased in term of coarse-grain scale. Also, the operating frequency is increase to lGHz by configuring Phase-Locked Loop (PLL). Furthermore, an acceptable image enhancement is obtained by applying tuning process on implemented
algorithms.
