A study on critical to functional parameters of flip chip die bonding technology in semiconductor industrial needs

As a multidisciplinary branch of engineering, microelectronic packaging involves the study of various methods of joining components to substrate in addition to interconnecting materials. Die attach technology, which connects the die and device to the rest of the system, plays an important role to ensure the entire system works consistently. Flip chip (FC) technology was developed by IBM in early 1960s for their solid logic technology. Die bonding techniques vary according to the requirements of the application of the packaged devices. Critical to functional (CTF) parameters of FC die bonding technologies such as adhesive bonding, solder reflow bonding, thermosonic bonding and thermo-compression bonding are crucial for any manufacturing floor involved in this backend assembly. In this work a comprehensive tabulation of all these FC bonding process was formed. Two pronged approach was used to obtain this information. The main prong approach was to embark a simulation based experiment to study the semiconductor package stress during the FC bonding process. The other supplementary approach used a systematic literature review (SLR), where all the critical to functional (CTF) parameters were identified, appraised and synthesized from the available cornucopia of the backend assembly in the semiconductor process world. In the simulation experiment, open source software Elmer was utilized for each varied parameter from substrate type, die thickness and process temperature. The results of the simulation shows higher stress in FC package with thicker die and higher process temperature. Increase in stiffness of thicker die amplified the strain induced in interconnect caused by coefficient of thermal expansion (CTE) mismatch. Similarly the stress elevated at higher bonding temperature as a result of expansion that happened within the semiconductor package. In addition, material thermal properties of each substrate type also contributes to the overall maximum package stress. Range of maximum package stress for respective FC bonding method: Solder reflow from 5.36E+08 N/m2 to 7.38E+08 N/m2; Adhesive from 3.77E+08 N/m2 to 5.57E+08 N/m2; Thermosonic from 2.21E+08 N/m2 to 9.48E+08 N/m2; TCB from 4.77E+08 N/m2 to 1.09E+09 N/m2. The output from SLR were documented into 1) FC process technology, 2) package geometry, 3) machine parameter, 4) FC process reliability, 5) bonding equipment as well as 6) challenges and future. Finally, this compositions of varied spectrum of CTF parameters were tabulated together for each respective FC bonding process. The findings in this research work will provide a comprehensive knowledge of the flip chip die bonding technology and easier for future research work as to improve the efficiency of any of the die bonding techniques.