Subash Chandra Bose Gopinath
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Preferred name
Subash Chandra Bose Gopinath
Official Name
Subash Chandra Bose, Gopinath
Alternative Name
Gopinath, S.
Gopinath, S. C.B
Subash Gopinath, C. B.
Subash, Gopinath
Subash C. B. Gopinath
Main Affiliation
Scopus Author ID
7006558013
Researcher ID
D-2953-2015

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  • Publication
    Failure analysis on silicon semiconductor device materials: Optical and high-resolution microscopic assessments
    ( 2022)
    Subash Chandra Bose Gopinath
    ;
    Santheraleka Ramanathan
    ;
    Mohd Najib Mohd Yasin
    ;
    Syahrizal Salleh
    ;
    Mohd Ibrahim Shapiai Razak
    ;
    Zool Hilmi Ismail
    ;
    Zaliman Sauli
    ;
    Sreeramanan Subramaniam
    ;
    M.B. Malarvili
    Defects of silicon (Si) semiconductor epilayers are crucial to be identified at laboratory environs. The identification of failure and its rectification at laboratory settings is essential for large-scaling manufacturing of narrowed down semiconductor devices. This research documented the inspection, identification and the solution for defects found in the Si semiconductor epilayers, fabricated by a simple and conventional photolithography technique, with the integration of metal oxide nanomaterial, zinc oxide (ZnO). The semiconductor epilayers, Si wafer, Si oxide and ZnO coated SiO2 layer were formed and examined. Optical microscope images [high power microscope (HPM) and 3D profilometer] reveal smooth surface of semiconductor epilayers development through thermal oxidation and photolithography techniques. High power ultraviolet-visible (UV-Vis) justified the accuracy of wet thermal oxidation by examining the thickness of oxide layer on Si wafer at 3837.3 A. The X-ray diffraction (XRD) analysis of sol-gel synthesized ZnO affirmed the hexagonal crystalline state and its nanoscale size at 54 nm. Field emission scanning electron microscopy (FESEM) has shown the insight of Si epilayer morphology with its elemental composition, which provides details of foreign substances on semiconductor surface. ZnO deposited Si epilayer was prepared through lamella preparation, prior to the cross-sectional field emission transmission electron microscopy (FETEM) analysis of the semiconductor, which revealed the uniformity of fabrication and ZnO distribution at Si epilayer. Failure analysis reported several defects on the Si epilayers in the state of patches and accumulation of impurities. The potential cause of the defects and the respective solutions are discussed as the accuracy and handling must be ensured throughout the fabrication process, to develop a flawless semiconductor for high performance. applications.